SNVU886 September   2024 TPS37100-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5.     General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  6. 2Hardware
    1. 2.1 EVM Connectors
      1. 2.1.1 EVM Jumpers
      2. 2.1.2 EVM Test Points
    2. 2.2 EVM Setup and Operation
      1. 2.2.1 Input Supply Voltage (VDD)
      2. 2.2.2 SENSE
      3. 2.2.3 OUT A and OUT B
      4. 2.2.4 AEN & AOUT
      5. 2.2.5 Built-In Self-Test (BIST)
      6. 2.2.6 Built-In Self-Test Enable (BIST_EN )
      7. 2.2.7 CTR & CTS Time Delays
  7. 3Implementation Results
    1. 3.1 EVM Performance Results
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1.     Trademarks
  10. 6Revision History

2.2.7 CTR & CTS Time Delays

The TPS3710X-Q1 family of devices contain an adjustable reset time delay pin (CTR) that controls the time with which both the OUT A pin and OUT B pin de-asserts after reaching the valid condition. The user can adjust the configuration of this pin via the jumper located at J5.

The TPS37100-Q1 family of devices contain an adjustable sense time delay pin (CTS) that controls the time with which both the OUT A and OUT B asserts after reaching the invalid condition. The user can adjust the configuration of this pin via the jumper located at J6. Refer to Section 2.1.1 for jumper connections and TPS37100-Q1 data sheet for capacitor values and sense delay timing.

Table 2-4 show the calculated typical delay values for the capacitor options on the TPS3710XEVM.

Table 2-4 Delay Options

Capacitor Values

Calculated Delay
CTS & CTR = 33nF 119ms
CTS & CTR = 100nF 360ms
CTS & CTR = 1uF 3.6s