SNVU886 September   2024 TPS37100-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5.     General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  6. 2Hardware
    1. 2.1 EVM Connectors
      1. 2.1.1 EVM Jumpers
      2. 2.1.2 EVM Test Points
    2. 2.2 EVM Setup and Operation
      1. 2.2.1 Input Supply Voltage (VDD)
      2. 2.2.2 SENSE
      3. 2.2.3 OUT A and OUT B
      4. 2.2.4 AEN & AOUT
      5. 2.2.5 Built-In Self-Test (BIST)
      6. 2.2.6 Built-In Self-Test Enable (BIST_EN )
      7. 2.2.7 CTR & CTS Time Delays
  7. 3Implementation Results
    1. 3.1 EVM Performance Results
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1.     Trademarks
  10. 6Revision History

2.2.3 OUT A and OUT B

The TPS3710X-Q1 family has two reset output pin; OUT A and OUT B connected through TP5 and TP7 on the board.

Table 2-3 Output Behaviors
Window VariantUV only VariantOV Only Variant
OUT AAsserts only when OV events happen

Both OUT A and OUT B asserts when an UV event happens

Both OUT A and OUT B asserts when an OV event happens
OUT BAsserts only when UV events happen

For window variants, to assert the OUT A or OUT B the sense pins needs to meet one of the conditions below:

  • •For OUT A, the SENSE voltage need to cross the lower boundary (VITP).
  • • For OUT B, the SENSE voltage needs to cross the upper boundary (VITN).

For UV only variants, to assert the OUT A or OUT B the sense pins needs to meet the condition below:

  • • For OUT A and OUT B, the SENSE voltage need to cross the lower boundary (VITN).

For OV only variants, to assert the OUT A or OUT B the sense pins needs to meet the condition below:

  • • For OUT A and OUT B, the SENSE voltage needs to cross the upper boundary (VITP)

Both the output pins are active-low and open-drain output.