Figure 4-10 shows the top layer of the PCB with layer 2 as a power-loop ground return path directly underneath the top layer to create a low-area switching power loop of approximately 2mm². This loop area, and hence parasitic inductance, must be as small as possible to minimize switch-node voltage overshoot and ringing (and hence the overall EMI signature).

As shown in Figure 4-11, the high-frequency power loop current flows through MOSFETs Q3 and Q4, through the power ground plane on layer 2, and back to VIN through the 0603 ceramic capacitors C30 through C33. The currents flowing in opposing directions in the vertical loop configuration provide field self-cancellation, reducing parasitic loop inductance. Figure 4-12 shows a side view to illustrate the concept of creating a low-profile, self-canceling loop in a multilayer PCB structure. The layer-2 GND plane layer, shown in Figure 4-11, provides a tightly-coupled current return path directly under the MOSFETs to the source terminals of Q4.

Four 10nF input capacitors with small 0603 case size place in parallel close to the drain of each high-side MOSFET. The low ESL and high self-resonant frequency (SRF) of the small footprint capacitors yield excellent high-frequency performance. The negative terminals of these capacitors connect to the layer-2 GND plane with multiple 12mil (0.3mm) diameter vias, further reducing parasitic inductance.

The following list describes additional important steps in a layout design. Refer to the LM5137-Q1 Automotive, 4V to 80V, 100% Duty Cycle Capable, Dual-Channel Synchronous Buck Controller Family for Functional Safety Applications data sheet layout guidelines for more detail.

• Keep the SW connection from the power MOSFETs to the inductor (for each channel) at minimum copper area to reduce capacitive coupling and radiated EMI.
• Position the IC between the two phase and relatively close to the power MOSFET gate terminals. Route the gate drive traces short and direct, and keep HO and SW traces together to minimize gate loop parasitic inductance.
• Create an analog ground plane near the IC for sensitive analog components. Connect the AGND plane and the PGND power ground planes at a single point at the die attach pad (DAP) of the IC.
• Route the current sense traces from the shunt to the IC as a differential pair and keep away from noise sources, such as the switch node and gate drive traces. Increase the width of the trace to the BIAS1/VOUT1 pin, as the trace carries the bias current for the IC.