SNVU912 June 2024 LP87524-Q1

1 Introduction

This technical reference manual can be used as a reference for the LP875241S-Q1 default register bits after OTP memory download. This technical reference manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the LP8752x-Q1 Four-Phase 10-A Buck Converter With Integrated Switches data sheet

Table 1-1 lists the main OTP settings for power rails. Table 2-1 lists the register bits loaded from OTP memory.

Table 1-1 Main OTP Settings for Power Rails

Description		Bit Name	LP875241S-Q1 Value
Device identification	OTP configuration	OTP_ID	0x19
BUCK0	Output voltage	BUCK0_VSET	900 mV
	Enable, EN pin, or I²C register	EN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECT	EN1
	Force PWM	BUCK0_FPWM	Yes
	Peak current limit	ILIM0	3.5 A
	Maximum load current	N/A	2.5 A
	Slew rate	SLEW_RATE0	1.9 mV/µs
BUCK1	Output voltage	BUCK1_VSET	900 mV
	Enable, EN pin, or I²C register	EN_BUCK1, EN_PIN_CTRL1, BUCK1_EN_PIN_SELECT	EN1
	Force PWM	BUCK1_FPWM	Yes
	Peak current limit	ILIM1	3.5 A
	Maximum load current	N/A	2.5 A
	Slew Rate	SLEW_RATE1	1.9 mV/µs
BUCK2	Output voltage	BUCK2_VSET	900 mV
	Enable, EN pin, or I²C register	EN_BUCK2, EN_PIN_CTRL2, BUCK2_EN_PIN_SELECT	EN3
	Force PWM	BUCK2_FPWM	Yes
	Peak current limit	ILIM2	4 A
	Maximum load current	N/A	3 A
	Slew rate	SLEW_RATE2	1.9 mV/µs
BUCK3	Output voltage	BUCK3_VSET	1000 mV
	Enable, EN pin, or I²C register	EN_BUCK3, EN_PIN_CTRL3, BUCK3_EN_PIN_SELECT	EN3
	Force PWM	BUCK3_FPWM	Yes
	Peak current limit	ILIM3	3.5 A
	Maximum load current	N/A	2.5 A
	Slew rate	SLEW_RATE3	1.9 mV/µs
Switching frequency		N/A	2 MHz
I²C address		N/A	0x60

Note:

The maximum total output capacitance (local + POL) per phase (BUCK0, BUCK1, BUCK2, and BUCK3) depends on the slew rate setting. Check the data sheet for the allowed capacitance value.