SNVU925 October 2024 LP5811
Table 2-40 lists the memory-mapped registers for the Autonomous_DC registers. All register offset addresses not listed in Table 2-40 should be considered as reserved locations and the register contents should not be modified.
Auto_DC_0 is shown in Figure 2-31 and described in Table 2-41.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
auto_dc_0 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | auto_dc_0 | R/W | 0h | LED_0 current setting in autonomous mode 0h = 0 1h = 0.39% 2h = 0.78% ... 80h = 50.2% ... FDh = 99.2% FEh = 99.6% FFh = 100% |
Auto_DC_1 is shown in Figure 2-32 and described in Table 2-42.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
auto_dc_1 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | auto_dc_1 | R/W | 0h | LED_1 current setting in autonomous mode 0h = 0 1h = 0.39% 2h = 0.78% ... 80h = 50.2% ... FDh = 99.2% FEh = 99.6% FFh = 100% |
Auto_DC_2 is shown in Figure 2-33 and described in Table 2-43.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
auto_dc_2 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | auto_dc_2 | R/W | 0h | LED_2 current setting in autonomous mode 0h = 0 1h = 0.39% 2h = 0.78% ... 80h = 50.2% ... FDh = 99.2% FEh = 99.6% FFh = 100% |
Auto_DC_3 is shown in Figure 2-34 and described in Table 2-44.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
auto_dc_3 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | auto_dc_3 | R/W | 0h | LED_3 current setting in autonomous mode 0h = 0 1h = 0.39% 2h = 0.78% ... 80h = 50.2% ... FDh = 99.2% FEh = 99.6% FFh = 100% |