SNVU925 October 2024 LP5811
Table 2-28 lists the memory-mapped registers for the Reset registers. All register offset addresses not listed in Table 2-28 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
23h | Reset | Software reset | Go |
Reset is shown in Figure 2-22 and described in Table 2-29.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sw_reset | |||||||
W1C-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | sw_reset | W1C | 0h | Software reset Write 66h to reset |