SNVU925 October 2024 LP5811
Table 2-35 lists the memory-mapped registers for the Manual_PWM registers. All register offset addresses not listed in Table 2-35 should be considered as reserved locations and the register contents should not be modified.
Manual_PWM_0 is shown in Figure 2-27 and described in Table 2-36.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
manual_pwm_0 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | manual_pwm_0 | R/W | 0h | LED_0 PWM setting in manual mode 0h = 0 1h = 0.39% 2h = 0.78% ... 80h = 50.2% ... FDh = 99.2% FEh = 99.6% FFh = 100% |
Manual_PWM_1 is shown in Figure 2-28 and described in Table 2-37.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
manual_pwm_1 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | manual_pwm_1 | R/W | 0h | LED_1 PWM setting in manual mode 0h = 0 1h = 0.39% 2h = 0.78% ... 80h = 50.2% ... FDh = 99.2% FEh = 99.6% FFh = 100% |
Manual_PWM_2 is shown in Figure 2-29 and described in Table 2-38.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
manual_pwm_2 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | manual_pwm_2 | R/W | 0h | LED_2 PWM setting in manual mode 0h = 0 1h = 0.39% 2h = 0.78% ... 80h = 50.2% ... FDh = 99.2% FEh = 99.6% FFh = 100% |
Manual_PWM_3 is shown in Figure 2-30 and described in Table 2-39.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
manual_pwm_3 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | manual_pwm_3 | R/W | 0h | LED_3 PWM setting in manual mode 0h = 0 1h = 0.39% 2h = 0.78% ... 80h = 50.2% ... FDh = 99.2% FEh = 99.6% FFh = 100% |