SNVU925 October 2024 LP5811
Table 2-2 lists the memory-mapped registers for the Device_Enable registers. All register offset addresses not listed in Table 2-2 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | Chip_EN | Enable the internal circuits | Go |
Chip_EN is shown in Figure 2-1 and described in Table 2-3.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | chip_en | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | RESERVED | R | 0h | Reserved |
0 | chip_en | R/W | 0h | Enable the internal circuits 0h = Disable 1h = Enable |