SPMA086 October   2022 TM4C1230C3PM , TM4C1230C3PM , TM4C1230D5PM , TM4C1230D5PM , TM4C1230E6PM , TM4C1230E6PM , TM4C1230H6PM , TM4C1230H6PM , TM4C1231C3PM , TM4C1231C3PM , TM4C1231D5PM , TM4C1231D5PM , TM4C1231D5PZ , TM4C1231D5PZ , TM4C1231E6PM , TM4C1231E6PM , TM4C1231E6PZ , TM4C1231E6PZ , TM4C1231H6PGE , TM4C1231H6PGE , TM4C1231H6PM , TM4C1231H6PM , TM4C1231H6PZ , TM4C1231H6PZ , TM4C1232C3PM , TM4C1232C3PM , TM4C1232D5PM , TM4C1232D5PM , TM4C1232E6PM , TM4C1232E6PM , TM4C1232H6PM , TM4C1232H6PM , TM4C1233C3PM , TM4C1233C3PM , TM4C1233D5PM , TM4C1233D5PM , TM4C1233D5PZ , TM4C1233D5PZ , TM4C1233E6PM , TM4C1233E6PM , TM4C1233E6PZ , TM4C1233E6PZ , TM4C1233H6PGE , TM4C1233H6PGE , TM4C1233H6PM , TM4C1233H6PM , TM4C1233H6PZ , TM4C1233H6PZ , TM4C1236D5PM , TM4C1236D5PM , TM4C1236E6PM , TM4C1236E6PM , TM4C1236H6PM , TM4C1236H6PM , TM4C1237D5PM , TM4C1237D5PM , TM4C1237D5PZ , TM4C1237D5PZ , TM4C1237E6PM , TM4C1237E6PM , TM4C1237E6PZ , TM4C1237E6PZ , TM4C1237H6PGE , TM4C1237H6PGE , TM4C1237H6PM , TM4C1237H6PM , TM4C1237H6PZ , TM4C1237H6PZ , TM4C123AE6PM , TM4C123AE6PM , TM4C123AH6PM , TM4C123AH6PM , TM4C123BE6PM , TM4C123BE6PM , TM4C123BE6PZ , TM4C123BE6PZ , TM4C123BH6PGE , TM4C123BH6PGE , TM4C123BH6PM , TM4C123BH6PM , TM4C123BH6PZ , TM4C123BH6PZ , TM4C123BH6ZRB , TM4C123BH6ZRB , TM4C123FE6PM , TM4C123FE6PM , TM4C123FH6PM , TM4C123FH6PM , TM4C123GE6PM , TM4C123GE6PM , TM4C123GE6PZ , TM4C123GE6PZ , TM4C123GH6PGE , TM4C123GH6PGE , TM4C123GH6PM , TM4C123GH6PM , TM4C123GH6PZ , TM4C123GH6PZ , TM4C123GH6ZRB , TM4C123GH6ZRB , TM4C123GH6ZXR , TM4C123GH6ZXR , TM4C1290NCPDT , TM4C1290NCPDT , TM4C1290NCZAD , TM4C1290NCZAD , TM4C1292NCPDT , TM4C1292NCPDT , TM4C1292NCZAD , TM4C1292NCZAD , TM4C1294KCPDT , TM4C1294KCPDT , TM4C1294NCPDT , TM4C1294NCPDT , TM4C1294NCZAD , TM4C1294NCZAD , TM4C1297NCZAD , TM4C1297NCZAD , TM4C1299KCZAD , TM4C1299KCZAD , TM4C1299NCZAD , TM4C1299NCZAD , TM4C129CNCPDT , TM4C129CNCPDT , TM4C129CNCZAD , TM4C129CNCZAD , TM4C129DNCPDT , TM4C129DNCPDT , TM4C129DNCZAD , TM4C129DNCZAD , TM4C129EKCPDT , TM4C129EKCPDT , TM4C129ENCPDT , TM4C129ENCPDT , TM4C129ENCZAD , TM4C129ENCZAD , TM4C129LNCZAD , TM4C129LNCZAD , TM4C129XKCZAD , TM4C129XKCZAD , TM4C129XNCZAD , TM4C129XNCZAD

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2How to Install
    1. 2.1 Update the FreeRTOS Version in the TivaWare Directory
    2. 2.2 Adding FreeRTOS Hardware Driver Files for TM4C LaunchPads
  5. 3Architecture for TM4C FreeRTOS Examples
    1. 3.1 Proper Clock Configuration
    2. 3.2 How to use Hardware Interrupts Alongside the FreeRTOS Kernel
  6. 4Example Project Walkthroughs
    1. 4.1 Download and Import the Examples
    2. 4.2 CAN Examples
      1. 4.2.1 multi_can_rx
      2. 4.2.2 multi_can_tx
    3. 4.3 Hardware Timer Examples
      1. 4.3.1 timer_edge_capture
      2. 4.3.2 timer_edge_count
    4. 4.4 I2C Examples
      1. 4.4.1 i2c_simple_loopback
      2. 4.4.2 i2c_tmp117_demo
    5. 4.5 PWM Examples
      1. 4.5.1 pwm_interrupt
      2. 4.5.2 pwm_invert
    6. 4.6 SSI Examples
      1. 4.6.1 ssi_simple_xfer
      2. 4.6.2 ssi_quad_mode
    7. 4.7 μDMA Examples
      1. 4.7.1 adc_udma_pingpong
      2. 4.7.2 udma_mem_transfer

4.7.1 adc_udma_pingpong

This example demonstrates how to use the ADC peripheral with both the μDMA and hardware timer peripherals to optimize the ADC sampling process for a single channel using the μDMA in Ping-Pong mode. One ADC channel is configured to convert an ADC input and the result is transferred via the μDMA to a buffer. Using Ping-Pong mode allows for the smooth swapping of buffers to ensure data is always being stored while also offering the application time to process a filled buffer. The timer is used to trigger the ADC measurements at a set sampling frequency of 16 kHz.

In this example, only one task is created that handles the processing of ADC conversion data. When μDMA completes the block transfer of ADC data to the buffers, it sends a notification to the processing task. The processing task takes the average of all samples and display on the terminal window. Afterwards, it signals to the μDMA controller that the buffer is ready for the next swap.