SPNA239 September   2019 RM46L440 , RM46L450 , RM46L830 , RM46L840 , RM46L850 , RM46L852 , RM48L530 , RM48L540 , RM48L730 , RM48L740 , RM48L940 , RM48L950 , RM48L952 , RM57L843 , TMS570LC4357 , TMS570LC4357-EP , TMS570LC4357-SEP , TMS570LS0232 , TMS570LS0332 , TMS570LS0432 , TMS570LS10106 , TMS570LS10116 , TMS570LS10206 , TMS570LS1114 , TMS570LS1115 , TMS570LS1224 , TMS570LS1225 , TMS570LS1227 , TMS570LS20206 , TMS570LS20206-EP , TMS570LS20216 , TMS570LS20216-EP , TMS570LS2124 , TMS570LS2125 , TMS570LS2134 , TMS570LS2135 , TMS570LS3134 , TMS570LS3135 , TMS570LS3137 , TMS570LS3137-EP

 

  1.   HALCoGen Ethernet Driver With lwIP Integration Demo and Active Web Server Demo
    1.     Trademarks
    2. 1 Introduction
    3. 2 Supported Features
    4. 3 Get the Software
    5. 4 Configuring EMAC and MDIO Using HALCoGen GUI for the lwIP Demo
      1. 4.1 RM46x, RM48x and TMS570LSx HDK
      2. 4.2 TMS570LC43x and RM57x HDK
      3. 4.3 RM57x Launchpad (LAUNCHXL2 RM57x)
      4. 4.4 TMS570LC43 Launchpad (LAUNCHXL2 570LC43x)
    6. 5 Additional Changes for Active Web Server Demo
      1. 5.1 HALCoGen Configuration Changes
      2. 5.2 lwIP Port Changes
      3. 5.3 CCS Project Structure
      4. 5.4 Changing the Web Pages Rendered by Web Server
    7. 6 Programming Sequence Using HALCoGen Generated Drivers
    8. 7 Design of lwIP Integration
      1. 7.1 Hardware Abstraction Layer
      2. 7.2 lwIP Interface Layer
      3. 7.3 Hercules Development Network Interface Layer
        1. 7.3.1 Network Device Initialization
        2. 7.3.2 Packet Data Transmission
        3. 7.3.3 Packet Data Reception
      4. 7.4 lwIP Application Layer
      5. 7.5 System Application Layer
    9. 8 Release Folder Structure
    10. 9 Run the Test
      1. 9.1 Hardware Setup
      2. 9.2 Building and Executing the lwIP Demo
      3. 9.3 Building and Executing the Active Web Server Demo
        1. 9.3.1 I/O Control Demo 1
        2. 9.3.2 I/O Control Demo 2

4.2 TMS570LC43x and RM57x HDK

  1. Under the ‘Driver Enable’ tab, enable EMAC Driver and SCI1 Driver.
  2. Under ‘VIM RAM’ add the names of the ISRs for EMAC Transmit and Receive Interrupts (Channels 77 and 79, respectively).
  3. Enable these interrupts under the ‘VIM Channel 64-95’ tab.
  4. Under the ‘PLL’ tab, change the multiplier for both PLLs to a value of 150, such that the output frequency in both cases is 300.00 MHz.
  5. Under the ‘GCM’ tab, change the value of the VCLK1, VCLK2 and VCLK3 Dividers to 1 and VCLKA4 Divider to 2, such that the output of VCLKA4_DIV is 37.50 MHz.
  6. Under the ‘PINMUX’ tab, enable RMII/MII, under Pin Muxing. Under Input Muxing, enable MDIO(G3), MII_COL(F3), MII_CRS(B4), MII_RX_DV(B11), MII_RX_ER(N19), MII_RXCLK(K19), MII_RXD[0], MII_RXD[1], MII_RXD[2], MII_RXD[3], MII_TX_CLK.
  7. Under the ‘EMAC’ tab, change the EMAC address to the correct address (the default one in the example is mentioned above). The physical address is 1 by default.
  8. Generate the system initialization and HAL Code.