SPNS176C April   2012  – June 2015 RM48L530 , RM48L730

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PGE QFP Package Pinout (144-Pin)
    2. 4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array)
    3. 4.3 Terminal Functions
      1. 4.3.1 PGE Package
        1. 4.3.1.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.3.1.2  Enhanced Next Generation High-End Timer (N2HET) Modules
        3. 4.3.1.3  General-Purpose Input/Output (GPIO)
        4. 4.3.1.4  Controller Area Network Controllers (DCANs)
        5. 4.3.1.5  Local Interconnect Network Interface Module (LIN)
        6. 4.3.1.6  Standard Serial Communication Interface (SCI)
        7. 4.3.1.7  Inter-Integrated Circuit Interface Module (I2C)
        8. 4.3.1.8  Standard Serial Peripheral Interface (SPI)
        9. 4.3.1.9  Multibuffered Serial Peripheral Interface Modules (MibSPI)
        10. 4.3.1.10 USB Host and Device Port Controller Interface
        11. 4.3.1.11 System Module Interface
        12. 4.3.1.12 Clock Inputs and Outputs
        13. 4.3.1.13 Test and Debug Modules Interface
        14. 4.3.1.14 Flash Supply and Test Pads
        15. 4.3.1.15 Supply for Core Logic: 1.2-V Nominal
        16. 4.3.1.16 Supply for I/O Cells: 3.3-V Nominal
        17. 4.3.1.17 Ground Reference for All Supplies Except VCCAD
      2. 4.3.2 ZWT Package
        1. 4.3.2.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.3.2.2  Enhanced Next Generation High-End Timer (N2HET) Modules
        3. 4.3.2.3  General-Purpose Input/Output (GPIO)
        4. 4.3.2.4  Controller Area Network Controllers (DCANs)
        5. 4.3.2.5  Local Interconnect Network Interface Module (LIN)
        6. 4.3.2.6  Standard Serial Communication Interface (SCI)
        7. 4.3.2.7  Inter-Integrated Circuit Interface Module (I2C)
        8. 4.3.2.8  Standard Serial Peripheral Interface (SPI)
        9. 4.3.2.9  Multibuffered Serial Peripheral Interface Modules (MibSPI)
        10. 4.3.2.10 USB Host and Device Port Controller Interface
        11. 4.3.2.11 External Memory Interface (EMIF)
        12. 4.3.2.12 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
        13. 4.3.2.13 RAM Trace Port (RTP)
        14. 4.3.2.14 Data Modification Module (DMM)
        15. 4.3.2.15 System Module Interface
        16. 4.3.2.16 Clock Inputs and Outputs
        17. 4.3.2.17 Test and Debug Modules Interface
        18. 4.3.2.18 Flash Supply and Test Pads
        19. 4.3.2.19 Reserved
        20. 4.3.2.20 No Connects
        21. 4.3.2.21 Supply for Core Logic: 1.2-V Nominal
        22. 4.3.2.22 Supply for I/O Cells: 3.3-V Nominal
        23. 4.3.2.23 Ground Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Switching Characteristics for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption
    8. 5.8  Input/Output Electrical Characteristics
    9. 5.9  Thermal Resistance Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
    13. 5.13 Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low-Power Oscillator (LPO)
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Master/Slave Access Privileges
        1. 6.9.3.1 Special Notes on Accesses to Certain Slaves
      4. 6.9.4 POM Overlay Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Flash Program and Erase Timings for Program Flash
      6. 6.10.6 Flash Program and Erase Timings for Data Flash
    11. 6.11 Tightly Coupled RAM (TCRAM) Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAM Interface ECC Support
    12. 6.12 Parity Protection for Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Asynchronous RAM
        2. 6.14.2.2 Synchronous Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 DMA Controller
      1. 6.16.1 DMA Features
      2. 6.16.2 Default DMA Request Map
    17. 6.17 Real Time Interrupt Module
      1. 6.17.1 Features
      2. 6.17.2 Block Diagrams
      3. 6.17.3 Clock Source Options
      4. 6.17.4 Network Time Synchronization Inputs
    18. 6.18 Error Signaling Module
      1. 6.18.1 Features
      2. 6.18.2 ESM Channel Assignments
    19. 6.19 Reset / Abort / Error Sources
    20. 6.20 Digital Windowed Watchdog
    21. 6.21 Debug Subsystem
      1. 6.21.1  Block Diagram
      2. 6.21.2  Debug Components Memory Map
      3. 6.21.3  JTAG Identification Code
      4. 6.21.4  Debug ROM
      5. 6.21.5  JTAG Scan Interface Timings
      6. 6.21.6  Advanced JTAG Security Module
      7. 6.21.7  Embedded Trace Macrocell (ETM-R4)
        1. 6.21.7.1 ETM TRACECLKIN Selection
        2. 6.21.7.2 Timing Specifications
      8. 6.21.8  RAM Trace Port (RTP)
        1. 6.21.8.1 Features
        2. 6.21.8.2 Timing Specifications
      9. 6.21.9  Data Modification Module (DMM)
        1. 6.21.9.1 Features
        2. 6.21.9.2 Timing Specifications
      10. 6.21.10 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Peripheral Legend
    2. 7.2  Multibuffered 12-Bit Analog-to-Digital Converter
      1. 7.2.1 Features
      2. 7.2.2 Event Trigger Options
        1. 7.2.2.1 Default MIBADC1 Event Trigger Hookup
        2. 7.2.2.2 Alternate MIBADC1 Event Trigger Hookup
        3. 7.2.2.3 Default MIBADC2 Event Trigger Hookup
        4. 7.2.2.4 Alternate MIBADC2 Event Trigger Hookup
      3. 7.2.3 ADC Electrical and Timing Specifications
      4. 7.2.4 Performance (Accuracy) Specifications
        1. 7.2.4.1 MibADC Nonlinearity Errors
        2. 7.2.4.2 MibADC Total Error
    3. 7.3  General-Purpose Input/Output
      1. 7.3.1 Features
    4. 7.4  Enhanced Next Generation High-End Timer (N2HET)
      1. 7.4.1 Features
      2. 7.4.2 N2HET RAM Organization
      3. 7.4.3 Input Timing Specifications
      4. 7.4.4 N2HET1-N2HET2 Interconnections
      5. 7.4.5 N2HET Checking
        1. 7.4.5.1 Internal Monitoring
        2. 7.4.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
      6. 7.4.6 Disabling N2HET Outputs
      7. 7.4.7 High-End Timer Transfer Unit (HTU)
        1. 7.4.7.1 Features
        2. 7.4.7.2 Trigger Connections
    5. 7.5  Controller Area Network (DCAN)
      1. 7.5.1 Features
      2. 7.5.2 Electrical and Timing Specifications
    6. 7.6  Local Interconnect Network Interface (LIN)
      1. 7.6.1 LIN Features
    7. 7.7  Serial Communication Interface (SCI)
      1. 7.7.1 Features
    8. 7.8  Inter-Integrated Circuit (I2C)
      1. 7.8.1 Features
      2. 7.8.2 I2C I/O Timing Specifications
    9. 7.9  Multibuffered / Standard Serial Peripheral Interface
      1. 7.9.1 Features
      2. 7.9.2 MibSPI Transmit and Receive RAM Organization
      3. 7.9.3 MibSPI Transmit Trigger Events
        1. 7.9.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.9.3.2 MIBSPI3 Event Trigger Hookup
        3. 7.9.3.3 MIBSPI5 Event Trigger Hookup
      4. 7.9.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.9.5 SPI Slave Mode I/O Timings
    10. 7.10 Universal Serial Bus (USB) Host and Device Controllers
      1. 7.10.1 Features
      2. 7.10.2 Electrical and Timing Specifications
  8. 8Device and Documentation Support
    1. 8.1  Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2  Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
    3. 8.3  Related Links
    4. 8.4  Community Resources
    5. 8.5  Trademarks
    6. 8.6  Electrostatic Discharge Caution
    7. 8.7  Glossary
    8. 8.8  Device Identification Code Register
    9. 8.9  Die Identification Registers
    10. 8.10 Module Certifications
      1. 8.10.1 DCAN Certification
      2. 8.10.2 LIN Certification
        1. 8.10.2.1 LIN Master Mode
        2. 8.10.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.10.2.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

2 Revision History

This data manual revision history highlights the technical changes made to the SPNS176B device-specific data manual to make it an SPNS176C revision.

Scope: Applicable updates to the Hercules™ RM MCU device family, specifically relating to the RM48Lx30 devices, which are now in the production data (PD) stage of development have been incorporated.

Changes from May 15, 2015 to June 30, 2015 (from B Revision (May 2015) to C Revision)

  • Figure 8-1 (RM48x Device Numbering Conventions): Updated/Changed figure to show the die revision letterGo