SPNS183C September   2012  – June 2015 RM46L440 , RM46L840

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PGE QFP Package Pinout (144-Pin)
    2. 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
    3. 4.3 Terminal Functions
      1. 4.3.1 PGE Package
        1. 4.3.1.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 4.3.1.2  Enhanced High-End Timer Modules (N2HET)
        3. 4.3.1.3  Enhanced Capture Modules (eCAP)
        4. 4.3.1.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.3.1.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.3.1.6  General-Purpose Input / Output (GPIO)
        7. 4.3.1.7  Controller Area Network Controllers (DCAN)
        8. 4.3.1.8  Local Interconnect Network Interface Module (LIN)
        9. 4.3.1.9  Standard Serial Communication Interface (SCI)
        10. 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.3.1.11 Standard Serial Peripheral Interface (SPI)
        12. 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.3.1.13 Ethernet Controller
        14. 4.3.1.14 System Module Interface
        15. 4.3.1.15 Clock Inputs and Outputs
        16. 4.3.1.16 Test and Debug Modules Interface
        17. 4.3.1.17 Flash Supply and Test Pads
        18. 4.3.1.18 Supply for Core Logic: 1.2V nominal
        19. 4.3.1.19 Supply for I/O Cells: 3.3V nominal
        20. 4.3.1.20 Ground Reference for All Supplies Except VCCAD
      2. 4.3.2 ZWT Package
        1. 4.3.2.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 4.3.2.2  Enhanced High-End Timer Modules (N2HET)
        3. 4.3.2.3  Enhanced Capture Modules (eCAP)
        4. 4.3.2.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.3.2.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.3.2.6  General-Purpose Input / Output (GPIO)
        7. 4.3.2.7  Controller Area Network Controllers (DCAN)
        8. 4.3.2.8  Local Interconnect Network Interface Module (LIN)
        9. 4.3.2.9  Standard Serial Communication Interface (SCI)
        10. 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.3.2.11 Standard Serial Peripheral Interface (SPI)
        12. 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.3.2.13 Ethernet Controller
        14. 4.3.2.14 External Memory Interface (EMIF)
        15. 4.3.2.15 System Module Interface
        16. 4.3.2.16 Clock Inputs and Outputs
        17. 4.3.2.17 Test and Debug Modules Interface
        18. 4.3.2.18 Flash Supply and Test Pads
        19. 4.3.2.19 Reserved
        20. 4.3.2.20 No Connects
        21. 4.3.2.21 Supply for Core Logic: 1.2V nominal
        22. 4.3.2.22 Supply for I/O Cells: 3.3V nominal
        23. 4.3.2.23 Ground Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings Over Operating Free-Air Temperature Range
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Device Recommended Operating Conditions
    5. 5.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption Over Recommended Operating Conditions
    8. 5.8  Input/Output Electrical Characteristics Over Recommended Operating Conditions
    9. 5.9  Thermal Resistance Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
    13. 5.13 Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate clock tree after GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low Power Oscillator
          1. 6.6.1.2.1 Features
        3. 6.6.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
        3. 6.6.2.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
      5. 6.9.5 Special Notes on Accesses to Certain Slaves
      6. 6.9.6 Parameter Overlay Module (POM) Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Program Flash
      6. 6.10.6 Data Flash
    11. 6.11 Tightly Coupled RAM Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAM ECC Support
    12. 6.12 Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Asynchronous RAM
        2. 6.14.2.2 Synchronous Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 DMA Controller
      1. 6.16.1 DMA Features
      2. 6.16.2 Default DMA Request Map
    17. 6.17 Real Time Interrupt Module
      1. 6.17.1 Features
      2. 6.17.2 Block Diagrams
      3. 6.17.3 Clock Source Options
      4. 6.17.4 Network Time Synchronization Inputs
    18. 6.18 Error Signaling Module
      1. 6.18.1 Features
      2. 6.18.2 ESM Channel Assignments
    19. 6.19 Reset / Abort / Error Sources
    20. 6.20 Digital Windowed Watchdog
    21. 6.21 Debug Subsystem
      1. 6.21.1 Block Diagram
      2. 6.21.2 Debug Components Memory Map
      3. 6.21.3 JTAG Identification Code
      4. 6.21.4 Debug ROM
      5. 6.21.5 JTAG Scan Interface Timings
      6. 6.21.6 Advanced JTAG Security Module
      7. 6.21.7 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Enhanced Translator PWM Modules (ePWM)
      1. 7.1.1 ePWM Clocking and Reset
      2. 7.1.2 Synchronization of ePWMx Time Base Counters
      3. 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.1.5 ePWM Synchronization with External Devices
      6. 7.1.6 ePWM Trip Zones
        1. 7.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.1.6.2 Trip Zone TZ4n
        3. 7.1.6.3 Trip Zone TZ5n
        4. 7.1.6.4 Trip Zone TZ6n
      7. 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
    2. 7.2  Enhanced Capture Modules (eCAP)
      1. 7.2.1 Clock Enable Control for eCAPx Modules
      2. 7.2.2 PWM Output Capability of eCAPx
      3. 7.2.3 Input Connection to eCAPx Modules
      4. 7.2.4 Enhanced Capture Module (eCAP) Timings
    3. 7.3  Enhanced Quadrature Encoder (eQEP)
      1. 7.3.1 Clock Enable Control for eQEPx Modules
      2. 7.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.3.3 Input Connections to eQEPx Modules
      4. 7.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    4. 7.4  Multibuffered 12bit Analog-to-Digital Converter
      1. 7.4.1 Features
      2. 7.4.2 Event Trigger Options
        1. 7.4.2.1 MIBADC1 Event Trigger Hookup
        2. 7.4.2.2 MIBADC2 Event Trigger Hookup
        3. 7.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.4.3 ADC Electrical and Timing Specifications
      4. 7.4.4 Performance (Accuracy) Specifications
        1. 7.4.4.1 MibADC Nonlinearity Errors
        2. 7.4.4.2 MibADC Total Error
    5. 7.5  General-Purpose Input/Output
      1. 7.5.1 Features
    6. 7.6  Enhanced High-End Timer (N2HET)
      1. 7.6.1 Features
      2. 7.6.2 N2HET RAM Organization
      3. 7.6.3 Input Timing Specifications
      4. 7.6.4 N2HET1-N2HET2 Synchronization
      5. 7.6.5 N2HET Checking
        1. 7.6.5.1 Internal Monitoring
        2. 7.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
      6. 7.6.6 Disabling N2HET Outputs
      7. 7.6.7 High-End Timer Transfer Unit (HTU)
        1. 7.6.7.1 Features
        2. 7.6.7.2 Trigger Connections
    7. 7.7  Controller Area Network (DCAN)
      1. 7.7.1 Features
      2. 7.7.2 Electrical and Timing Specifications
    8. 7.8  Local Interconnect Network Interface (LIN)
      1. 7.8.1 LIN Features
    9. 7.9  Serial Communication Interface (SCI)
      1. 7.9.1 Features
    10. 7.10 Inter-Integrated Circuit (I2C)
      1. 7.10.1 Features
      2. 7.10.2 I2C I/O Timing Specifications
    11. 7.11 Multibuffered / Standard Serial Peripheral Interface
      1. 7.11.1 Features
      2. 7.11.2 MibSPI Transmit and Receive RAM Organization
      3. 7.11.3 MibSPI Transmit Trigger Events
        1. 7.11.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.11.3.2 MIBSPI3 Event Trigger Hookup
        3. 7.11.3.3 MIBSPI5 Event Trigger Hookup
      4. 7.11.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.11.5 SPI Slave Mode I/O Timings
    12. 7.12 Ethernet Media Access Controller
      1. 7.12.1 Ethernet MII Electrical and Timing Specifications
      2. 7.12.2 Ethernet RMII Electrical and Timing Specifications
      3. 7.12.3 Management Data Input/Output (MDIO)
  8. 8Device and Documentation Support
    1. 8.1 Device and Development-Support Tool Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
      2. 8.2.2 Related Links
      3. 8.2.3 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
    6. 8.6 Device Identification
      1. 8.6.1 Device Identification Code Register
      2. 8.6.2 Die Identification Registers
    7. 8.7 Module Certifications
      1. 8.7.1 DCAN Certification
      2. 8.7.2 LIN Certification
        1. 8.7.2.1 LIN Master Mode
        2. 8.7.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.7.2.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

2 Revision History

This data manual revision history highlights the technical changes made to the SPNS183B device-specific data manual to make it an SPNS183C revision.

Scope: Applicable updates to the Hercules™ RM MCU device family, specifically relating to the RM46Lx40 devices, which are now in the production data (PD) stage of development have been incorporated.

Changes from March 14, 2015 to June 30, 2015 (from B Revision (March 2015) to C Revision)

  • Section 1.3 (Description): Corrected DMA description, 32 peripheral requests, not 32 control packetsGo
  • Table 4-18 (PGE Test and Debug Modules Interface): Specified size of pulldown on TDO during resetGo
  • Table 4-41 (ZWT Test and Debug Modules Interface): Specified size of pulldown on TDO during resetGo
  • Section 6.5.1 (Summary of ARM Cortex-R4F CPU Features): Added quantity of breakpoints and watchpoints Go
  • Table 6-21 (Device Memory Map): Corrected Bank 7 OTP sizeGo
  • Section 7.11.1 ([MibSPI] Features): Corrected size of SPI baud rate generator, 11 bit, not 8 bit Go
  • Figure 8-1 (RM46Lx40 Device Numbering Conventions): Updated/Changed figure to show the die revision letter.Go