SPNS184C September   2012  – June 2015 RM46L450 , RM46L850

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PGE QFP Package Pinout (144-Pin)
    2. 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
    3. 4.3 Terminal Functions
      1. 4.3.1 PGE Package
        1. 4.3.1.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 4.3.1.2  Enhanced High-End Timer Modules (N2HET)
        3. 4.3.1.3  Enhanced Capture Modules (eCAP)
        4. 4.3.1.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.3.1.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.3.1.6  General-Purpose Input / Output (GPIO)
        7. 4.3.1.7  Controller Area Network Controllers (DCAN)
        8. 4.3.1.8  Local Interconnect Network Interface Module (LIN)
        9. 4.3.1.9  Standard Serial Communication Interface (SCI)
        10. 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.3.1.11 Standard Serial Peripheral Interface (SPI)
        12. 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.3.1.13 Ethernet Controller
        14. 4.3.1.14 USB Host and Device Port Controller Interface
        15. 4.3.1.15 System Module Interface
        16. 4.3.1.16 Clock Inputs and Outputs
        17. 4.3.1.17 Test and Debug Modules Interface
        18. 4.3.1.18 Flash Supply and Test Pads
        19. 4.3.1.19 Supply for Core Logic: 1.2V nominal
        20. 4.3.1.20 Supply for I/O Cells: 3.3V nominal
        21. 4.3.1.21 Ground Reference for All Supplies Except VCCAD
      2. 4.3.2 ZWT Package
        1. 4.3.2.1  Multibuffered Analog-to-Digital Converters (MibADC)
        2. 4.3.2.2  Enhanced High-End Timer Modules (N2HET)
        3. 4.3.2.3  Enhanced Capture Modules (eCAP)
        4. 4.3.2.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.3.2.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.3.2.6  General-Purpose Input / Output (GPIO)
        7. 4.3.2.7  Controller Area Network Controllers (DCAN)
        8. 4.3.2.8  Local Interconnect Network Interface Module (LIN)
        9. 4.3.2.9  Standard Serial Communication Interface (SCI)
        10. 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.3.2.11 Standard Serial Peripheral Interface (SPI)
        12. 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.3.2.13 Ethernet Controller
        14. 4.3.2.14 USB Host and Device Port Controller Interface
        15. 4.3.2.15 External Memory Interface (EMIF)
        16. 4.3.2.16 System Module Interface
        17. 4.3.2.17 Clock Inputs and Outputs
        18. 4.3.2.18 Test and Debug Modules Interface
        19. 4.3.2.19 Flash Supply and Test Pads
        20. 4.3.2.20 Reserved
        21. 4.3.2.21 No Connects
        22. 4.3.2.22 Supply for Core Logic: 1.2V nominal
        23. 4.3.2.23 Supply for I/O Cells: 3.3V nominal
        24. 4.3.2.24 Ground Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings Over Operating Free-Air Temperature Range
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Device Recommended Operating Conditions
    5. 5.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption Over Recommended Operating Conditions
    8. 5.8  Input/Output Electrical Characteristics Over Recommended Operating Conditions
    9. 5.9  Thermal Resistance Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
    13. 5.13 Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate clock tree after GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low Power Oscillator
          1. 6.6.1.2.1 Features
        3. 6.6.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
        3. 6.6.2.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
      5. 6.9.5 Special Notes on Accesses to Certain Slaves
      6. 6.9.6 Parameter Overlay Module (POM) Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Program Flash
      6. 6.10.6 Data Flash
    11. 6.11 Tightly Coupled RAM Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAM ECC Support
    12. 6.12 Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Asynchronous RAM
        2. 6.14.2.2 Synchronous Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 DMA Controller
      1. 6.16.1 DMA Features
      2. 6.16.2 Default DMA Request Map
    17. 6.17 Real Time Interrupt Module
      1. 6.17.1 Features
      2. 6.17.2 Block Diagrams
      3. 6.17.3 Clock Source Options
      4. 6.17.4 Network Time Synchronization Inputs
    18. 6.18 Error Signaling Module
      1. 6.18.1 Features
      2. 6.18.2 ESM Channel Assignments
    19. 6.19 Reset / Abort / Error Sources
    20. 6.20 Digital Windowed Watchdog
    21. 6.21 Debug Subsystem
      1. 6.21.1 Block Diagram
      2. 6.21.2 Debug Components Memory Map
      3. 6.21.3 JTAG Identification Code
      4. 6.21.4 Debug ROM
      5. 6.21.5 JTAG Scan Interface Timings
      6. 6.21.6 Advanced JTAG Security Module
      7. 6.21.7 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Enhanced Translator PWM Modules (ePWM)
      1. 7.1.1 ePWM Clocking and Reset
      2. 7.1.2 Synchronization of ePWMx Time Base Counters
      3. 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.1.5 ePWM Synchronization with External Devices
      6. 7.1.6 ePWM Trip Zones
        1. 7.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.1.6.2 Trip Zone TZ4n
        3. 7.1.6.3 Trip Zone TZ5n
        4. 7.1.6.4 Trip Zone TZ6n
      7. 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
    2. 7.2  Enhanced Capture Modules (eCAP)
      1. 7.2.1 Clock Enable Control for eCAPx Modules
      2. 7.2.2 PWM Output Capability of eCAPx
      3. 7.2.3 Input Connection to eCAPx Modules
      4. 7.2.4 Enhanced Capture Module (eCAP) Timings
    3. 7.3  Enhanced Quadrature Encoder (eQEP)
      1. 7.3.1 Clock Enable Control for eQEPx Modules
      2. 7.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.3.3 Input Connections to eQEPx Modules
      4. 7.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    4. 7.4  Multibuffered 12bit Analog-to-Digital Converter
      1. 7.4.1 Features
      2. 7.4.2 Event Trigger Options
        1. 7.4.2.1 MIBADC1 Event Trigger Hookup
        2. 7.4.2.2 MIBADC2 Event Trigger Hookup
        3. 7.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.4.3 ADC Electrical and Timing Specifications
      4. 7.4.4 Performance (Accuracy) Specifications
        1. 7.4.4.1 MibADC Nonlinearity Errors
        2. 7.4.4.2 MibADC Total Error
    5. 7.5  General-Purpose Input/Output
      1. 7.5.1 Features
    6. 7.6  Enhanced High-End Timer (N2HET)
      1. 7.6.1 Features
      2. 7.6.2 N2HET RAM Organization
      3. 7.6.3 Input Timing Specifications
      4. 7.6.4 N2HET1-N2HET2 Synchronization
      5. 7.6.5 N2HET Checking
        1. 7.6.5.1 Internal Monitoring
        2. 7.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
      6. 7.6.6 Disabling N2HET Outputs
      7. 7.6.7 High-End Timer Transfer Unit (HTU)
        1. 7.6.7.1 Features
        2. 7.6.7.2 Trigger Connections
    7. 7.7  Controller Area Network (DCAN)
      1. 7.7.1 Features
      2. 7.7.2 Electrical and Timing Specifications
    8. 7.8  Local Interconnect Network Interface (LIN)
      1. 7.8.1 LIN Features
    9. 7.9  Serial Communication Interface (SCI)
      1. 7.9.1 Features
    10. 7.10 Inter-Integrated Circuit (I2C)
      1. 7.10.1 Features
      2. 7.10.2 I2C I/O Timing Specifications
    11. 7.11 Multibuffered / Standard Serial Peripheral Interface
      1. 7.11.1 Features
      2. 7.11.2 MibSPI Transmit and Receive RAM Organization
      3. 7.11.3 MibSPI Transmit Trigger Events
        1. 7.11.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.11.3.2 MIBSPI3 Event Trigger Hookup
        3. 7.11.3.3 MIBSPI5 Event Trigger Hookup
      4. 7.11.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.11.5 SPI Slave Mode I/O Timings
    12. 7.12 Ethernet Media Access Controller
      1. 7.12.1 Ethernet MII Electrical and Timing Specifications
      2. 7.12.2 Ethernet RMII Electrical and Timing Specifications
      3. 7.12.3 Management Data Input/Output (MDIO)
    13. 7.13 Universal Serial Bus (USB) Host and Device Controllers
      1. 7.13.1 Features
      2. 7.13.2 Electrical and Timing Specifications
  8. 8Device and Documentation Support
    1. 8.1 Device and Development-Support Tool Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
      2. 8.2.2 Related Links
      3. 8.2.3 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
    6. 8.6 Device Identification
      1. 8.6.1 Device Identification Code Register
      2. 8.6.2 Die Identification Registers
    7. 8.7 Module Certifications
      1. 8.7.1 DCAN Certification
      2. 8.7.2 LIN Certification
        1. 8.7.2.1 LIN Master Mode
        2. 8.7.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.7.2.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

7 Peripheral Information and Electrical Specifications

7.1 Enhanced Translator PWM Modules (ePWM)

Figure 7-1 illustrates the connections between the seven ePWM modules (ePWM1,2,3,4,5,6,7) on the device.

RM46L450 RM46L850 eTPWMx_interconnections_spns185.gifFigure 7-1 ePWMx Module Interconnections

7.1.1 ePWM Clocking and Reset

Each ePWM module has a clock enable (EPWMxENCLK). When SYS_nRST is active low, the clock enables are ignored and the ePWM logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the state of clock enable is respected.

Table 7-1 ePWMx Clock Enable Control

ePWM Module Instance Control Register to Enable Clock Default Value
ePWM1 PINMMR37[8] 1
ePWM2 PINMMR37[16] 1
ePWM3 PINMMR37[24] 1
ePWM4 PINMMR38[0] 1
ePWM5 PINMMR38[8] 1
ePWM6 PINMMR38[16] 1
ePWM7 PINMMR38[24] 1

The default value of the control registers to enable the clocks to the ePWMx modules is 1. This means that the VCLK4 clock connections to the ePWMx modules are enabled by default. The application can choose to gate off the VCLK4 clock to any ePWMx module individually by clearing the respective control register bit.

7.1.2 Synchronization of ePWMx Time Base Counters

A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The input synchronization for the first instance (ePWM1) comes from an external pin. Figure 7-1 shows the synchronization connections for all the ePWMx modules. Each ePWM module can be configured to use or ignore the synchronization input. Refer to the ePWM chapter in the RM46x Technical Reference Manual (SPNU514) for more information.

7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base

The connection between the N2HET1_LOOP_SYNC and SYNCI input of ePWM1 module is implemented as shown in Figure 7-2.

RM46L450 RM46L850 sychonizing_tpwmx_n2het_spns185.gifFigure 7-2 Synchronizing Time Bases Between N2HET1, N2HET2 and ePWMx Modules

7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules

The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM modules on a device. This bit is implemented as PINMMR37 register bit 1.

When TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped. This is the default condition.

When TBCLKSYNC = 1, all ePWM time-base clocks are started with the rising edge of TBCLK aligned.

For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must be set identically. The proper procedure for enabling the ePWM clocks is as follows:

  1. Enable the individual ePWM module clocks (if disable) using the control registers shown in Table 7-1.
  2. Configure TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.
  3. Configure the prescaler values and desired ePWM modes.
  4. Configure TBCLKSYNC = 1.

7.1.5 ePWM Synchronization with External Devices

The output sync from EPWM1 Module is also exported to a device output terminal so that multiple devices can be synchronized together. The signal pulse is stretched by eight VCLK4 cycles before being exported on the terminal as the EPWM1SYNCO signal.

7.1.6 ePWM Trip Zones

The ePWMx modules have six trip zone inputs each. These are active-low signals. The application can control the ePWMx module response to each of the trip zone input separately. The timing requirements from the assertion of the trip zone inputs to the actual response are specified in Section 7.1.8.

7.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n

These three trip zone inputs are driven by external circuits and are connected to device-level inputs. These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-synchronized with VCLK4, or double-synchronized and then filtered with a 6-cycle VCLK4-based counter before connecting to the ePWMx. By default, the trip zone inputs are asynchronously connected to the ePWMx modules.

Table 7-2 Connection to ePWMx Modules for Device-Level Trip Zone Inputs

Trip Zone Input Control for Asynchronous Connection to ePWMx Control for Double-Synchronized Connection to ePWMx Control for Double-Synchronized and Filtered Connection to ePWMx
TZ1n PINMMR46[16] = 1 PINMMR46[16] = 0 AND PINMMR46[17] = 1 PINMMR46[16] = 0 AND PINMMR46[17] = 0 AND PINMMR46[18] = 1
TZ2n PINMMR46[24] = 1 PINMMR46[24] = 0 AND PINMMR46[25] = 1 PINMMR46[24] = 0 AND PINMMR46[25] = 0 AND PINMMR46[26] = 1
TZ3n PINMMR47[0] = 1 PINMMR47[0] = 0 AND PINMMR47[1] = 1 PINMMR47[0] = 0 AND PINMMR47[1] = 0 AND PINMMR47[2] = 1

7.1.6.2 Trip Zone TZ4n

This trip zone input is dedicated to eQEPx error indications. There are two eQEP modules on this device. Each eQEP module indicates a phase error by driving its EQEPxERR output High. The following control registers allow the application to configure the trip zone input (TZ4n) to each ePWMx module based on the application’s requirements.

Table 7-3 TZ4n Connections for ePWMx Modules

ePWMx Control for TZ4n = not(EQEP1ERR OR EQEP2ERR) Control for TZ4n = not(EQEP1ERR) Control for TZ4n = not(EQEP2ERR)
ePWM1 PINMMR41[0] = 1 PINMMR41[0] = 0 AND PINMMR41[1] = 1 PINMMR41[0] = 1 AND PINMMR41[1] = 0 AND PINMMR41[2] = 1
ePWM2 PINMMR41[8] PINMMR41[8] = 0 AND PINMMR41[9] = 1 PINMMR41[8] = 1 AND PINMMR41[9] = 0 AND PINMMR41[10] = 1
ePWM3 PINMMR41[16] PINMMR41[16] = 0 AND PINMMR41[17] = 1 PINMMR41[16] = 1 AND PINMMR41[17] = 0 AND PINMMR41[18] = 1
ePWM4 PINMMR41[24] PINMMR41[24] = 0 AND PINMMR41[25] = 1 PINMMR41[24] = 1 AND PINMMR41[25] = 0 AND PINMMR41[26] = 1
ePWM5 PINMMR42[0] PINMMR42[0] = 0 AND PINMMR42[1] = 1 PINMMR42[0] = 1 AND PINMMR42[1] = 0 AND PINMMR42[2] = 1
ePWM6 PINMMR42[8] PINMMR42[8] = 0 AND PINMMR42[9] = 1 PINMMR42[8] = 1 AND PINMMR42[9] = 0 AND PINMMR42[10] = 1
ePWM7 PINMMR42[16] PINMMR42[16] = 0 AND PINMMR42[17] = 1 PINMMR42[16] = 1 AND PINMMR42[17] = 0 AND PINMMR42[18] = 1

7.1.6.3 Trip Zone TZ5n

This trip zone input is dedicated to a clock failure on the device. That is, this trip zone input is asserted whenever an oscillator failure or a PLL slip is detected on the device. The application can use this trip zone input for each ePWMx module in order to prevent the external system from going out of control when the device clocks are not within expected range (system running at limp clock).

The oscillator failure and PLL slip signals used for this trip zone input are taken from the status flags in the system module. These are level signals are set until cleared by the application.

7.1.6.4 Trip Zone TZ6n

This trip zone input to the ePWMx modules is dedicated to a debug mode entry of the CPU. If enabled, the user can force the PWM outputs to a known state when the emulator stops the CPU. This prevents the external system from going out of control when the CPU is stopped.

7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs

A special scheme is implemented in order to select the actual signal used for triggering the start of conversion on the two ADCs on this device. This scheme is defined in Section 7.4.2.3.

7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings

Table 7-4 ePWMx Timing Requirements

PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(SYNCIN) Synchronization input pulse width Asynchronous 2 tc(VCLK4) cycles
Synchronous 2 tc(VCLK4) cycles
Synchronous, with input filter 2 tc(VCLK4) + filter width cycles

Table 7-5 ePWMx Switching Characteristics

PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(PWM) Pulse duration, ePWMx output high or low 33.33 ns
tw(SYNCOUT) Synchronization Output Pulse Width 8 tc(VCLK4) cycles
td(PWM)tza Delay time, trip input active to PWM forced high, OR Delay time, trip input active to PWM forced low no pin load 25 ns
td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns

Table 7-6 ePWMx Trip-Zone Timing Requirements

PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(TZ) Pulse duration, TZn input low Asynchronous 2 * HSPCLKDIV * CLKDIV * tc(VCLK4)(1) ns
Synchronous 2 tc(VCLK4) ns
Synchronous, with input filter 8 tc(VCLK4) ns
(1) Refer to the ePWM chapter of the RM46x Technical Reference Manual (SPNU514) for more information on the clock divider fields HSPCLKDIV and CLKDIV.

7.2 Enhanced Capture Modules (eCAP)

Figure 7-3 shows how the eCAP modules are interconnected on this microcontroller.

RM46L450 RM46L850 eCAP_connections_spns185.gifFigure 7-3 eCAP Module Connections

7.2.1 Clock Enable Control for eCAPx Modules

Each of the ECAPx modules have a clock enable (ECAPxENCLK). These signals need to be generated from a device-level control register. When SYS_nRST is active low, the clock enables are ignored and the ECAPx logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the state of clock enable is respected.

Table 7-7 eCAPx Clock Enable Control

ePWM Module Instance Control Register to Enable Clock Default Value
eCAP1 PINMMR39[0] 1
eCAP2 PINMMR39[8] 1
eCAP3 PINMMR39[16] 1
eCAP4 PINMMR39[24] 1
eCAP5 PINMMR40[0] 1
eCAP6 PINMMR40[8] 1

The default value of the control registers to enable the clocks to the eCAPx modules is 1. This means that the VCLK4 clock connections to the eCAPx modules are enabled by default. The application can choose to gate off the VCLK4 clock to any eCAPx module individually by clearing the respective control register bit.

7.2.2 PWM Output Capability of eCAPx

When not used in capture mode, each of the eCAPx modules can be used as a single-channel PWM output. This is called the auxiliary PWM (APWM) mode of operation of the eCAP modules. Refer to the eCAP chapter of the RM46x Technical Reference Manual (SPNU514) for more information.

7.2.3 Input Connection to eCAPx Modules

The input connection to each of the eCAP modules can be selected between a double-VCLK4-synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-8.

Table 7-8 Device-Level Input Connection to eCAPx Modules

Input Signal Control for Double-Synchronized Connection to eCAPx Control for Double-Synchronized and Filtered Connection to eCAPx
eCAP1 PINMMR43[0] = 1 PINMMR43[0] = 0 AND PINMMR43[1] = 1
eCAP2 PINMMR43[8] = 1 PINMMR43[8] = 0 AND PINMMR43[9] = 1
eCAP3 PINMMR43[16] = 1 PINMMR43[16] = 0 AND PINMMR43[17] = 1
eCAP4 PINMMR43[24] = 1 PINMMR43[24] = 0 AND PINMMR43[25] = 1
eCAP5 PINMMR44[0] = 1 PINMMR44[0] = 0 AND PINMMR44[1] = 1
eCAP6 PINMMR44[8] = 1 PINMMR44[8] = 0 AND PINMMR44[9] = 1

7.2.4 Enhanced Capture Module (eCAP) Timings

Table 7-9 eCAPx Timing Requirements

PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(CAP) Capture input pulse width Synchronous 2 tc(VCLK4) cycles
Synchronous, with input filter 2 tc(VCLK4) + filter width cycles

Table 7-10 eCAPx Switching Characteristics

PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(APWM) Pulse duration, APWMx output high or low 20 ns

7.3 Enhanced Quadrature Encoder (eQEP)

Figure 7-4 shows the eQEP module interconnections on the device.

RM46L450 RM46L850 eQEP_connections_spns185.gifFigure 7-4 eQEP Module Interconnections

7.3.1 Clock Enable Control for eQEPx Modules

Device-level control registers are implemented to generate the EQEPxENCLK signals. When SYS_nRST is active low, the clock enables are ignored and the eQEPx logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the state of clock enable is respected.

Table 7-11 eQEPx Clock Enable Control

ePWM Module Instance Control Register to Enable Clock Default Value
eQEP1 PINMMR40[16] 1
eQEP2 PINMMR40[24] 1

The default value of the control registers to enable the clocks to the eQEPx modules is 1. This means that the VCLK4 clock connections to the eQEPx modules are enabled by default. The application can choose to gate off the VCLK4 clock to any eQEPx module individually by clearing the respective control register bit.

7.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs

The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection multiplexor. This multiplexor is defined in Table 7-3. As shown in Figure 7-1, the output of this selection multiplexor is inverted and connected to the TZ4n trip-zone input of all EPWMx modules. This connection allows the application to define the response of each ePWMx module on a phase error indicated by the eQEP modules.

7.3.3 Input Connections to eQEPx Modules

The input connections to each of the eQEP modules can be selected between a double-VCLK4-synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-12.

Table 7-12 Device-Level Input Connection to eCAPx Modules

Input Signal Control for Double-Synchronized Connection to eQEPx Control for Double-Synchronized and Filtered Connection to eQEPx
eQEP1A PINMMR44[16] = 1 PINMMR44[16] = 0 and PINMMR44[17] = 1
eQEP1B PINMMR44[24] = 1 PINMMR44[24] = 0 and PINMMR44[25] = 1
eQEP1I PINMMR45[0] = 1 PINMMR45[0] = 0 and PINMMR45[1] = 1
eQEP1S PINMMR45[8] = 1 PINMMR45[8] = 0 and PINMMR45[9] = 1
eQEP2A PINMMR45[16] = 1 PINMMR45[16] = 0 and PINMMR45[17] = 1
eQEP2B PINMMR45[24] = 1 PINMMR45[24] = 0 and PINMMR45[25] = 1
eQEP2I PINMMR46[0] = 1 PINMMR46[0] = 0 and PINMMR46[1] = 1
eQEP2S PINMMR46[8] = 1 PINMMR46[8] = 0 and PINMMR46[9] = 1

7.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing

Table 7-13 eQEPx Timing Requirements

PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(QEPP) QEP input period Synchronous 2 tc(VCLK4) cycles
Synchronous, with input filter 2 tc(VCLK4) + filter width cycles
tw(INDEXH) QEP Index Input High Time Synchronous 2 tc(VCLK4) cycles
Synchronous, with input filter 2 tc(VCLK4) + filter width cycles
tw(INDEXL) QEP Index Input Low Time Synchronous 2 tc(VCLK4) cycles
Synchronous, with input filter 2 tc(VCLK4) + filter width cycles
tw(STROBH) QEP Strobe Input High Time Synchronous 2 tc(VCLK4) cycles
Synchronous, with input filter 2 tc(VCLK4) + filter width cycles
tw(STROBL) QEP Strobe Input Low Time Synchronous 2 tc(VCLK4) cycles
Synchronous, with input filter 2 tc(VCLK4) + filter width cycles

Table 7-14 eQEPx Switching Characteristics

PARAMETER MIN MAX UNIT
td(CNTR)xin Delay time, external clock to counter increment 4 tc(VCLK4) cycles
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6 tc(VCLK4) cycles

7.4 Multibuffered 12bit Analog-to-Digital Converter

The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO unless otherwise noted.

Table 7-15 MibADC Overview

Description Value
Resolution 12 bits
Monotonic Assured
Output conversion code 00h to 3FFh [00 for VAI ≤ ADREFLO; 3FFh for VAI ≥ ADREFHI]

7.4.1 Features

  • 12-bit resolution
  • ADREFHI and ADREFLO pins (high and low reference voltages)
  • Total Sample/Hold/Convert time: 600ns Minimum at 30MHz ADCLK
  • One memory region per conversion group is available (event, group 1, group 2)
  • Allocation of channels to conversion groups is completely programmable
  • Supports flexible channel conversion order
  • Memory regions are serviced either by interrupt or by DMA
  • Programmable interrupt threshold counter is available for each group
  • Programmable magnitude threshold interrupt for each group for any one channel
  • Option to read either 8-bit, 10-bit or 12-bit values from memory regions
  • Single or continuous conversion modes
  • Embedded self-test
  • Embedded calibration logic
  • Enhanced power-down mode
    • Optional feature to automatically power down ADC core when no conversion is in progress
  • External event pin (ADxEVT) programmable as general-purpose I/O

7.4.2 Event Trigger Options

The ADC module supports 3 conversion groups: Event Group, Group1 and Group2. Each of these 3 groups can be configured to be hardware event-triggered. In that case, the application can select from among 8 event sources to be the trigger for a group's conversions.

7.4.2.1 MIBADC1 Event Trigger Hookup

Table 7-16 MIBADC1 Event Trigger Hookup

Group Source Select, G1SRC, G2SRC or EVSRC Event # Trigger Event Signal
PINMMR30[0] = 1
(default)		 PINMMR30[0] = 0 and PINMMR30[1] = 1
Option A Control for Option A Option B Control for Option B
000 1 AD1EVT AD1EVT — AD1EVT —
001 2 N2HET1[8] N2HET2[5] PINMMR30[8] = 1 ePWM_B PINMMR30[8] = 0 and
PINMMR30[9] = 1
010 3 N2HET1[10] N2HET1[27] — N2HET1[27] —
011 4 RTI Compare 0 Interrupt RTI Compare 0 Interrupt PINMMR30[16] = 1 ePWM_A1 PINMMR30[16] = 0 and
PINMMR30[17] = 1
100 5 N2HET1[12] N2HET1[17] — N2HET1[17] —
101 6 N2HET1[14] N2HET1[19] PINMMR30[24] = 1 N2HET2[1] PINMMR30[24] = 0 and
PINMMR30[25] = 1
110 7 GIOB[0] N2HET1[11] PINMMR31[0] = 1 ePWM_A2 PINMMR31[0] = 0 and
PINMMR31[1] = 1
111 8 GIOB[1] N2HET2[13] PINMMR32[16] = 1 ePWM_AB PINMMR31[8] = 0 and
PINMMR31[9] = 1

NOTE

If ADEVT, N2HET1 or GIOB is used as a trigger source, the connection to the MibADC1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad (through the mux control), or by driving the function from an external trigger source as input. If the mux control module is used to select different functionality instead of the ADEVT, N2HET1[x] or GIOB[x] signals, then care must be taken to disable these signals from triggering conversions; there is no multiplexing on the input connections.

If ePWM_B, ePWM_S2, ePWM_AB, N2HET2[1], N2HET2[5], N2HET2[13], N2HET1[11], N2HET1[17] or N2HET1[19] is used to trigger the ADC the connection to the ADC is made directly from the N2HET or ePWM module outputs. As a result, the ADC can be triggered without having to enable the signal from being output on a device terminal.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU.

7.4.2.2 MIBADC2 Event Trigger Hookup

Table 7-17 MIBADC2 Event Trigger Hookup

Group Source Select, G1SRC, G2SRC or EVSRC Event # Trigger Event Signal
PINMMR30[0] = 1
(default)		 PINMMR30[0] = 0 and PINMMR30[1] = 1
Option A Control for Option A Option B Control for Option B
000 1 AD2EVT AD2EVT — AD2EVT —
001 2 N2HET1[8] N2HET2[5] PINMMR31[16] = 1 ePWM_B PINMMR31[16] = 0 and
PINMMR31[17] = 1
010 3 N2HET1[10] N2HET1[27] — N2HET1[27] —
011 4 RTI Compare 0 Interrupt RTI Compare 0 Interrupt PINMMR31[24] = 1 ePWM_A1 PINMMR31[24] = 0 and
PINMMR31[25] = 1
100 5 N2HET1[12] N2HET1[17] — N2HET1[17] —
101 6 N2HET1[14] N2HET1[19] PINMMR32[0] = 1 N2HET2[1] PINMMR32[0] = 0 and
PINMMR32[1] = 1
110 7 GIOB[0] N2HET1[11] PINMMR32[8] = 1 ePWM_A2 PINMMR32[8] = 0 and
PINMMR32[9] = 1
111 8 GIOB[1] N2HET2[13] PINMMR32[16] = 1 ePWM_AB PINMMR32[16] = 0 and
PINMMR32[17] = 1

NOTE

If AD2EVT, N2HET1 or GIOB is used as a trigger source, the connection to the MibADC2 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad (through the mux control), or by driving the function from an external trigger source as input. If the mux control module is used to select different functionality instead of the AD2EVT, N2HET1[x] or GIOB[x] signals, then care must be taken to disable these signals from triggering conversions; there is no multiplexing on the input connections.

If ePWM_B, ePWM_S2, ePWM_AB, N2HET2[5], N2HET2[1], N2HET2[13], N2HET1[11], N2HET1[17] or N2HET1[19] is used to trigger the ADC the connection to the ADC is made directly from the N2HET or ePWM module outputs. As a result, the ADC can be triggered without having to enable the signal from being output on a device terminal.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU.

7.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules

As shown in Figure 7-5, the ePWMxSOCA and ePWMxSOCB outputs from each ePWM module are used to generate 4 signals – ePWM_B, ePWM_A1, ePWM_A2 and ePWM_AB, that are available to trigger the ADC based on the application requirement.

RM46L450 RM46L850 ADC_trigger_from_eTPWM_spns185.gifFigure 7-5 ADC Trigger Source Generation from ePWMx

Table 7-18 Control Bit to SOC Output

Control Bit SOC Output
PINMMR35[0] SOC1A_SEL
PINMMR35[8] SOC2A_SEL
PINMMR35[16] SOC3A_SEL
PINMMR35[24] SOC4A_SEL
PINMMR36[0] SOC5A_SEL
PINMMR36[8] SOC6A_SEL
PINMMR36[16] SOC7A_SEL

The SOCA output from each ePWM module is connected to a "switch" shown in Figure 7-5.

The logic equations for the 4 outputs from the combinational logic shown in Figure 7-5 are:
ePWM_B = SOC1B or SOC2B or SOC3B or SOC4B or SOC5B or SOC6B or SOC7B
ePWM_A1 = [ SOC1A and not(SOC1A_SEL) ] or [ SOC2A and not(SOC2A_SEL) ] or [ SOC3A and not(SOC3A_SEL) ] or
[ SOC4A and not(SOC4A_SEL) ] or [ SOC5A and not(SOC5A_SEL) ] or [ SOC6A and not(SOC6A_SEL) ] or
[ SOC7A and not(SOC7A_SEL) ]
ePWM_A2 = [ SOC1A and SOC1A_SEL ] or [ SOC2A and SOC2A_SEL ] or [ SOC3A and SOC3A_SEL ] or
[ SOC4A and SOC4A_SEL ] or [ SOC5A and SOC5A_SEL ] or [ SOC6A and SOC6A_SEL ] or
[ SOC7A and SOC7A_SEL ]
ePWM_AB = ePWM_B or ePWM_A2

7.4.3 ADC Electrical and Timing Specifications

Table 7-19 MibADC Recommended Operating Conditions

Parameter MIN MAX Unit
ADREFHI A-to-D high-voltage reference source ADREFLO VCCAD(1) V
ADREFLO A-to-D low-voltage reference source VSSAD(1) ADREFHI V
VAI Analog input voltage ADREFLO ADREFHI V
IAIK Analog input clamp current(2)
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)		 - 2 2 mA
(1) For VCCAD and VSSAD recommended operating conditions, see Section 5.4.
(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

Table 7-20 MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions

Parameter Description/Conditions MIN Nom MAX Unit
Rmux Analog input mux on-resistance See Figure 7-6 250 Ω
Rsamp ADC sample switch on-resistance See Figure 7-6 250 Ω
Cmux Input mux capacitance See Figure 7-6 16 pF
Csamp ADC sample capacitance See Figure 7-6 13 pF
IAIL Analog off-state input leakage current VCCAD = 3.6V maximum VSSAD ≤ VIN < VSSAD + 100mV -300 200 nA
VSSAD + 100mV ≤ VIN ≤ VCCAD - 200mV -200 200 nA
VCCAD - 200mV < VIN ≤ VCCAD -200 500 nA
IAIL Analog off-state input leakage current VCCAD = 5.5V maximum VSSAD ≤ VIN < VSSAD + 300mV -1000 250 nA
VSSAD + 300mV ≤ VIN ≤ VCCAD - 300mV -250 250 nA
VCCAD - 300mV < VIN ≤ VCCAD -250 1000 nA
IAOSB1(1) ADC1 Analog on-state input bias current VCCAD = 3.6V maximum VSSAD ≤ VIN < VSSAD + 100mV -8 2 µA
VSSAD + 100mV < VIN < VCCAD - 200mV -4 2 µA
VCCAD - 200mV < VIN < VCCAD -4 12 µA
IAOSB2(1) ADC2 Analog on-state input bias current VCCAD = 3.6V maximum VSSAD ≤ VIN < VSSAD + 100mV -7 2 µA
VSSAD + 100mV ≤ VIN ≤ VCCAD - 200mV -4 2 µA
VCCAD - 200mV < VIN ≤ VCCAD -4 10 µA
IAOSB1(1) ADC1 Analog on-state input bias current VCCAD = 5.5V maximum VSSAD ≤ VIN < VSSAD + 300mV -10 3 µA
VSSAD + 300mV ≤ VIN ≤ VCCAD - 300mV -5 3 µA
VCCAD - 300mV < VIN ≤ VCCAD -5 14 µA
IAOSB2(1) ADC2 Analog on-state input bias current VCCAD = 5.5V maximum VSSAD ≤ VIN < VSSAD + 300mV -8 3 µA
VSSAD + 300mV ≤ VIN ≤ VCCAD - 300mV -5 3 µA
VCCAD - 300mV < VIN ≤ VCCAD -5 12 µA
IADREFHI ADREFHI input current ADREFHI = VCCAD, ADREFLO = VSSAD 3 mA
ICCAD Static supply current Normal operating mode 15 mA
ADC core in power down mode 5 µA
(1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to IAOSB1 + IAOSB2
RM46L450 RM46L850 mibadc_circuit_pns160.gifFigure 7-6 MibADC Input Equivalent Circuit

Table 7-21 MibADC Timing Specifications

Parameter MIN NOM MAX Unit
tc(ADCLK)(2) Cycle time, MibADC clock 0.033 µs
td(SH)(3) Delay time, sample and hold time 0.2 µs
td(PU-ADV) Delay time from ADC power on until first input can be sampled 1 µs
12-bit mode
td©) Delay time, conversion time 0.4 µs
td(SHC)(1) Delay time, total sample/hold and conversion time 0.6 µs
10-bit mode
td©) Delay time, conversion time 0.33 µs
td(SHC)(1) Delay time, total sample/hold and conversion time 0.53 µs
(1) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, for example, the prescale settings.
(2) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits 4:0.
(3) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as well as the ADC’s internal impedance.

Table 7-22 MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions(1)(2)

Parameter Description/Conditions MIN Type MAX Unit
CR Conversion range over which specified accuracy is maintained ADREFHI - ADREFLO 3 5.5 V
ZSET Zero Scale Offset Difference between the first ideal transition (from code 000h to 001h) and the actual transition 10-bit mode 1 LSB
12-bit mode 2 LSB
FSET Full Scale Offset Difference between the range of the measured code transitions (from first to last) and the range of the ideal code transitions 10-bit mode 2 LSB
12-bit mode 3 LSB
EDNL Differential nonlinearity error Difference between the actual step width and the ideal value. (See Figure 7-7) 10-bit mode ± 1.5 LSB
12-bit mode ± 2 LSB
EINL Integral nonlinearity error Maximum deviation from the best straight line through the MibADC. MibADC transfer characteristics, excluding the quantization error. 10-bit mode ± 2 LSB
12-bit mode ± 2 LSB
ETOT Total unadjusted error Maximum value of the difference between an analog value and the ideal midstep value. 10-bit mode ± 2 LSB
12-bit mode ± 4 LSB
(1) 1 LSB = (ADREFHI – ADREFLO)/ 212 for 12-bit mode
(2) 1 LSB = (ADREFHI – ADREFLO)/ 210 for 10-bit mode

7.4.4 Performance (Accuracy) Specifications

7.4.4.1 MibADC Nonlinearity Errors

The differential nonlinearity error shown in Figure 7-7 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB.

RM46L450 RM46L850 dnl_error_pns160.gifFigure 7-7 Differential Nonlinearity (DNL) Error

The integral nonlinearity error shown in Figure 7-8 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line.

RM46L450 RM46L850 inl_error_pns160.gifFigure 7-8 Integral Nonlinearity (INL) Error

7.4.4.2 MibADC Total Error

The absolute accuracy or total error of an MibADC as shown in Figure 7-9 is the maximum value of the difference between an analog value and the ideal midstep value.

RM46L450 RM46L850 total_error_pns160.gifFigure 7-9 Absolute Accuracy (Total) Error

7.5 General-Purpose Input/Output

The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and bit-programmable. Both GIOA and GIOB support external interrupt capability.

7.5.1 Features

The GPIO module has the following features:

  • Each IO pin can be configured as:
    • Input
    • Output
    • Open Drain
  • The interrupts have the following characteristics:
    • Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)
    • Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)
    • Individual interrupt flags (set in GIOFLG register)
    • Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers respectively
    • Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers
  • Internal pullup/pulldown allows unused I/O pins to be left unconnected

For information on input and output timings see Section 5.11 and Section 5.12

7.6 Enhanced High-End Timer (N2HET)

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.

7.6.1 Features

The N2HET module has the following features:

  • Programmable timer for input and output timing functions
  • Reduced instruction set (30 instructions) for dedicated time and angle functions
  • 160 words of instruction RAM protected by parity
  • User defined number of 25-bit virtual counters for timer, event counters and angle counters
  • 7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual counters
  • Up to 32 pins usable for input signal measurements or output signal generation
  • Programmable suppression filter for each input pin with adjustable limiting frequency
  • Low CPU overhead and interrupt load
  • Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU) or DMA
  • Diagnostic capabilities with different loopback mechanisms and pin status read back functionality

7.6.2 N2HET RAM Organization

The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one RAM address may be written while another address is read. The RAM words are 96-bits wide, which are split into three 32-bit fields (program, control, and data).

7.6.3 Input Timing Specifications

All of the N2HET channels have an enhanced pulse capture circuit. The N2HET instructions PCNT and WCAP use this circuit to achieve the input timing requirements shown in Figure 7-10 and Table 7-23 below.

RM46L450 RM46L850 nhet_input_timings_pns160.gifFigure 7-10 N2HET Input Capture Timings

Table 7-23 Input Timing Requirements for N2HET Channels with Enhanced Pulse Capture

PARAMETER MIN MAX UNIT
1, 2 Input signal period, PCNT or WCAP (HRP) (LRP) tc(VCLK2) + 2 225 (HRP) (LRP) tc(VCLK2) - 2 ns
3 Input signal high phase, PCNT or WCAP 2 (HRP) tc(VCLK2) + 2 225 (HRP) (LRP) tc(VCLK2) - 2 ns
4 Input signal low phase, PCNT or WCAP 2 (HRP) tc(VCLK2) + 2 225 (HRP) (LRP) tc(VCLK2) - 2 ns

7.6.4 N2HET1-N2HET2 Synchronization

In some applications the N2HET resolutions must be synchronized. Some other applications require a single time base to be used for all PWM outputs and input timing captures.

The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to the loop resolution signal sent by the master. The slave does not require this signal after it receives the first synchronization signal. However, anytime the slave receives the re-synchronization signal from the master, the slave must synchronize itself again..

RM46L450 RM46L850 nhet_interconnect_pns160.gifFigure 7-11 N2HET1 – N2HET2 Synchronization Hookup

7.6.5 N2HET Checking

7.6.5.1 Internal Monitoring

To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be used to monitor each other’s signals as shown in Figure 7-12. The direction of the monitoring is controlled by the I/O multiplexing control module.

RM46L450 RM46L850 nhet_monitoring_pns160.gifFigure 7-12 N2HET Monitoring

7.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)

N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure the frequency of the pulse-width modulated (PWM) signal on N2HET1[31].

Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to measure the frequency of the pulse-width modulated (PWM) signal on N2HET2[0].

Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection to the DCC module is made directly from the output of the N2HETx module (from the input of the output buffer).

For more information on DCC see Section 6.7.3.

7.6.6 Disabling N2HET Outputs

Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET module provides this capability through the "Pin Disable" input signal. This signal, when driven low, causes the N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. For more details on the "N2HET Pin Disable" feature, see the device-specific Terminal Reference Manual.

GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin Disable" input for N2HET2.

7.6.7 High-End Timer Transfer Unit (HTU)

A High End Timer Transfer Unit (HTU) can perform DMA type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

7.6.7.1 Features

  • CPU and DMA independent
  • Master Port to access system memory
  • 8 control packets supporting dual buffer configuration
  • Control packet information is stored in RAM protected by parity
  • Event synchronization (HET transfer requests)
  • Supports 32 or 64 bit transactions
  • Addressing modes for HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or 64bit)
  • One shot, circular and auto switch buffer transfer modes
  • Request lost detection

7.6.7.2 Trigger Connections

Table 7-24 HTU1 Request Line Connection

Modules Request Source HTU1 Request
N2HET1 HTUREQ[0] HTU1 DCP[0]
N2HET1 HTUREQ[1] HTU1 DCP[1]
N2HET1 HTUREQ[2] HTU1 DCP[2]
N2HET1 HTUREQ[3] HTU1 DCP[3]
N2HET1 HTUREQ[4] HTU1 DCP[4]
N2HET1 HTUREQ[5] HTU1 DCP[5]
N2HET1 HTUREQ[6] HTU1 DCP[6]
N2HET1 HTUREQ[7] HTU1 DCP[7]

Table 7-25 HET TU2 Request Line Connection

Modules Request Source HET TU2 Request
N2HET2 HTUREQ[0] HTU2 DCP[0]
N2HET2 HTUREQ[1] HTU2 DCP[1]
N2HET2 HTUREQ[2] HTU2 DCP[2]
N2HET2 HTUREQ[3] HTU2 DCP[3]
N2HET2 HTUREQ[4] HTU2 DCP[4]
N2HET2 HTUREQ[5] HTU2 DCP[5]
N2HET2 HTUREQ[6] HTU2 DCP[6]
N2HET2 HTUREQ[7] HTU2 DCP[7]

7.7 Controller Area Network (DCAN)

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring.

7.7.1 Features

Features of the DCAN module include:

  • Supports CAN protocol version 2.0 part A, B
  • Bit rates up to 1 MBit/s
  • The CAN kernel can be clocked by the oscillator for baud-rate generation.
  • 64 mailboxes on each DCAN
  • Individual identifier mask for each message object
  • Programmable FIFO mode for message objects
  • Programmable loop-back modes for self-test operation
  • Automatic bus on after Bus-Off state by a programmable 32-bit timer
  • Message RAM protected by parity
  • Direct access to Message RAM during test mode
  • CAN Rx / Tx pins configurable as general purpose IO pins
  • Message RAM Auto Initialization
  • DMA support

For more information on the DCAN see the RM46x Technical Reference Manual (SPNU514).

7.7.2 Electrical and Timing Specifications

Table 7-26 Dynamic Characteristics for the DCANx TX and RX pins

Parameter MIN MAX Unit
td(CANnTX) Delay time, transmit shift register to CANnTX pin(1) 15 ns
td(CANnRX) Delay time, CANnRX pin to receive shift register 5 ns
(1) These values do not include rise/fall times of the output buffer.

7.8 Local Interconnect Network Interface (LIN)

The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility.

The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-line.

The LIN standard is based on the SCI (UART) serial data link format. The communication concept is single-master/multiple-slave with a message identification for multi-cast transmission between any network nodes.

7.8.1 LIN Features

The following are features of the LIN module:

  • Compatible to LIN 1.3, 2.0 and 2.1 protocols
  • Multibuffered receive and transmit units DMA capability for minimal CPU intervention
  • Identification masks for message filtering
  • Automatic Master Header Generation
    • Programmable Synch Break Field
    • Synch Field
    • Identifier Field
  • Slave Automatic Synchronization
    • Synch break detection
    • Optional baudrate update
    • Synchronization Validation
  • 231 programmable transmission rates with 7 fractional bits
  • Error detection
  • 2 Interrupt lines with priority encoding

7.9 Serial Communication Interface (SCI)

7.9.1 Features

  • Standard universal asynchronous receiver-transmitter (UART) communication
  • Supports full- or half-duplex operation
  • Standard nonreturn to zero (NRZ) format
  • Double-buffered receive and transmit functions
  • Configurable frame format of 3 to 13 bits per character based on the following:
    • Data word length programmable from one to eight bits
    • Additional address bit in address-bit mode
    • Parity programmable for zero or one parity bit, odd or even parity
    • Stop programmable for one or two stop bits
  • Asynchronous or isosynchronous communication modes
  • Two multiprocessor communication formats allow communication between more than two devices.
  • Sleep mode is available to free CPU resources during multiprocessor communication.
  • The 24-bit programmable baud rate supports 224 different baud rates provide high accuracy baud rate selection.
  • Four error flags and Five status flags provide detailed information regarding SCI events.
  • Capability to use DMA for transmit and receive data.

7.10 Inter-Integrated Circuit (I2C)

The inter-integrated circuit (I2C) module is a multi-master communication module providing an interface between the RM4x microcontroller and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2C-bus. This module will support any slave or master I2C compatible device.

7.10.1 Features

The I2C has the following features:

  • Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number 9398 393 40011)
    • Bit/Byte format transfer
    • 7-bit and 10-bit device addressing modes
    • General call
    • START byte
    • Multi-master transmitter/ slave receiver mode
    • Multi-master receiver/ slave transmitter mode
    • Combined master transmit/receive and receive/transmit mode
    • Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate)
  • Free data format
  • Two DMA events (transmit and receive)
  • DMA event enable/disable capability
  • Seven interrupts that can be used by the CPU
  • Module enable/disable capability
  • The SDA and SCL are optionally configurable as general purpose I/O
  • Slew rate control of the outputs
  • Open drain control of the outputs
  • Programmable pullup/pulldown capability on the inputs
  • Supports Ignore NACK mode

NOTE

This I2C module does not support:

  • High-speed (HS) mode
  • C-bus compatibility mode
  • The combined format in 10-bit address mode (the I2C sends the slave address second byte every time it sends the slave address first byte)

7.10.2 I2C I/O Timing Specifications

Table 7-27 I2C Signals (SDA and SCL) Switching Characteristics(1)

Parameter Standard Mode Fast Mode Unit
MIN MAX MIN MAX
tc(I2CCLK) Cycle time, Internal Module clock for I2C, prescaled from VCLK 75.2 149 75.2 149 ns
f(SCL) SCL Clock frequency 0 100 0 400 kHz
tc(SCL) Cycle time, SCL 10 2.5 µs
tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs
th(SCLL-SDAL) Hold time, SCL low after SDA low (for a repeated START condition) 4 0.6 µs
tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
tw(SCLH) Pulse duration, SCL high 4 0.6 µs
tsu(SDA-SCLH) Setup time, SDA valid before SCL high 250 100 ns
th(SDA-SCLL) Hold time, SDA valid after SCL low (for I2C bus devices) 0 3.45(2) 0 0.9 µs
tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs
tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4.0 0.6 µs
tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns
Cb(3) Capacitive load for each bus line 400 400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal.
(3) Cb = The total capacitance of one bus line in pF.
RM46L450 RM46L850 i2c_timing_pns160.gifFigure 7-13 I2C Timings

NOTE

  • A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
  • The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal.
  • A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH).
  • Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.

7.11 Multibuffered / Standard Serial Peripheral Interface

The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display drivers, and analog-to-digital converters.

7.11.1 Features

Both Standard and MibSPI modules have the following features:

  • 16-bit shift register
  • Receive buffer register
  • 11-bit baud clock generator
  • SPICLK can be internally-generated (master mode) or received from an external clock source (slave mode)
  • Each word transferred can have a unique format
  • SPI I/Os not used in the communication can be used as digital input/output signals

Table 7-28 MibSPI/SPI Configurations PGE Package

MibSPIx/SPIx I/Os
MibSPI1 MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:4,2:0], MIBSPI1nENA
MibSPI3 MIBSPI3SIMO[0], MIBSPI3SOMI[0], MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MibSPI5 MIBSPI5SIMO[0], MIBSPI5SOMI[2:0], MIBSPI5CLK, MIBSPI5nCS[0], MIBSPI5nENA
SPI4 SPI4SIMO[0], SPI4SOMI[0], SPI4CLK, SPI4nCS[0], SPI4nENA

Table 7-29 MibSPI/SPI Configurations ZWT Package

MibSPIx/SPIx I/Os
MibSPI1 MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA
MibSPI3 MIBSPI3SIMO[0], MIBSPI3SOMI[0], MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MibSPI5 MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[3:0], MIBSPI5nENA
SPI2 SPI2SIMO[0], SPI2SOMI[0], SPI2CLK, SPI2nCS[1:0], SPI2nENA
SPI4 SPI4SIMO[0], SPI4SOMI[0], SPI4CLK, SPI4nCS[0], SPI4nENA

7.11.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a 16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer RAM can be partitioned into multiple transfer group with variable number of buffers each. Each MibSPIx module supports 8 transfer groups.

7.11.3 MibSPI Transmit Trigger Events

Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low level at a selectable trigger source. For example, up to 15 trigger sources are available for use by each transfer group. These trigger options are listed in Table 7-30 and Section 7.11.3.2 for MibSPI1 and MibSPi3 respectively.

7.11.3.1 MIBSPI1 Event Trigger Hookup

Table 7-30 MIBSPI1 Event Trigger Hookup

Event # TGxCTRL TRIGSRC[3:0] Trigger
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 N2HET1[8]
EVENT9 1010 N2HET1[10]
EVENT10 1011 N2HET1[12]
EVENT11 1100 N2HET1[14]
EVENT12 1101 N2HET1[16]
EVENT13 1110 N2HET1[18]
EVENT14 1111 Internal Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving the GIOx pin from an external trigger source. If the mux control module is used to select different functionality instead of the GIOx signal, then care must be taken to disable GIOx from triggering MibSPI1 transfers; there is no multiplexing on the input connections.

7.11.3.2 MIBSPI3 Event Trigger Hookup

Table 7-31 MIBSPI3 Event Trigger Hookup

Event # TGxCTRL TRIGSRC[3:0] Trigger
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 N2HET1[8]
EVENT9 1010 N2HET1[10]
EVENT10 1011 N2HET1[12]
EVENT11 1100 N2HET1[14]
EVENT12 1101 N2HET1[16]
EVENT13 1110 N2HET1[18]
EVENT14 1111 Internal Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving the GIOx pin from an external trigger source. If the mux control module is used to select different functionality instead of the GIOx signal, then care must be taken to disable GIOx from triggering MibSPI3 transfers; there is no multiplexing on the input connections.

7.11.3.3 MIBSPI5 Event Trigger Hookup

Table 7-32 MIBSPI5 Event Trigger Hookup

Event # TGxCTRL TRIGSRC[3:0] Trigger
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 N2HET1[8]
EVENT9 1010 N2HET1[10]
EVENT10 1011 N2HET1[12]
EVENT11 1100 N2HET1[14]
EVENT12 1101 N2HET1[16]
EVENT13 1110 N2HET1[18]
EVENT14 1111 Internal Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving the GIOx pin from an external trigger source. If the mux control module is used to select different functionality instead of the GIOx signal, then care must be taken to disable GIOx from triggering MibSPI5 transfers; there is no multiplexing on the input connections.

7.11.4 MibSPI/SPI Master Mode I/O Timing Specifications

Table 7-33 SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)(1)(2)(3)

NO. Parameter MIN MAX Unit
1 tc(SPC)M Cycle time, SPICLK(4) 40 256tc(VCLK) ns
2(5) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns
tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
3(5) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 ns
tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
4(5) td(SPCH-SIMO)M Delay time, SPISIMO valid before SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 6 ns
td(SPCL-SIMO)M Delay time, SPISIMO valid before SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 6
5(5) tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC) – 4 ns
tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC) – 4
6(5) tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 0) tf(SPC) + 2.2 ns
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 1) tr(SPC) + 2.2
7(5) th(SPCL-SOMI)M Hold time, SPISOMI data valid after SPICLK low (clock polarity = 0) 10 ns
th(SPCH-SOMI)M Hold time, SPISOMI data valid after SPICLK high (clock polarity = 1) 10
8(6) tC2TDELAY Setup time CS active until SPICLK high (clock polarity = 0) CSHOLD = 0 C2TDELAY*tc(VCLK) + 2*tc(VCLK) - tf(SPICS) + tr(SPC) – 7 (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 ns
CSHOLD = 1 C2TDELAY*tc(VCLK) + 3*tc(VCLK) - tf(SPICS) + tr(SPC) – 7 (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5
Setup time CS active until SPICLK low (clock polarity = 1) CSHOLD = 0 C2TDELAY*tc(VCLK) + 2*tc(VCLK) - tf(SPICS) + tf(SPC) – 7 (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5 ns
CSHOLD = 1 C2TDELAY*tc(VCLK) + 3*tc(VCLK) - tf(SPICS) + tf(SPC) – 7 (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5
9(6) tT2CDELAY Hold time SPICLK low until CS inactive (clock polarity = 0) 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) - 7 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) + 11 ns
Hold time SPICLK high until CS inactive (clock polarity = 1) 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) - 7 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) + 11 ns
10 tSPIENA SPIENAn Sample point (C2TDELAY+1) * tc(VCLK) - tf(SPICS) – 29 (C2TDELAY+1)*tc(VCLK) ns
11 tSPIENAW SPIENAn Sample point from write to buffer (C2TDELAY+2)*tc(VCLK) ns
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see Table 5-7.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
RM46L450 RM46L850 master_mode_external_timing_phase0_pns160.gifFigure 7-14 SPI Master Mode External Timing (CLOCK PHASE = 0)
RM46L450 RM46L850 master_mode_chip_select_phase0_pns160.gifFigure 7-15 SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)

Table 7-34 SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)(1)(2)(3)

NO. Parameter MIN MAX Unit
1 tc(SPC)M Cycle time, SPICLK (4) 40 256tc(VCLK) ns
2(5) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns
tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
3(5) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 ns
tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
4(5) tv(SIMO-SPCH)M Valid time, SPICLK high after SPISIMO data valid (clock polarity = 0) 0.5tc(SPC)M – 6 ns
tv(SIMO-SPCL)M Valid time, SPICLK low after SPISIMO data valid (clock polarity = 1) 0.5tc(SPC)M – 6
5(5) tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC) – 4 ns
tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC) – 4
6(5) tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 0) tr(SPC) + 2.2 ns
tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 1) tf(SPC) + 2.2
7(5) tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) 10 ns
tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 10
8(6) tC2TDELAY Setup time CS active until SPICLK high (clock polarity = 0) CSHOLD = 0 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) – 7 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 ns
CSHOLD = 1 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) – 7 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5
Setup time CS active until SPICLK low (clock polarity = 1) CSHOLD = 0 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) – 7 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5 ns
CSHOLD = 1 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) – 7 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5
9(6) tT2CDELAY Hold time SPICLK low until CS inactive (clock polarity = 0) T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) - 7 T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) + 11 ns
Hold time SPICLK high until CS inactive (clock polarity = 1) T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) - 7 T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) + 11 ns
10 tSPIENA SPIENAn Sample Point (C2TDELAY+1)* tc(VCLK) - tf(SPICS) – 29 (C2TDELAY+1)*tc(VCLK) ns
11 tSPIENAW SPIENAn Sample point from write to buffer (C2TDELAY+2)*tc(VCLK) ns
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see the Table 5-7.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
RM46L450 RM46L850 master_mode_external_timing_phase1_pns160.gifFigure 7-16 SPI Master Mode External Timing (CLOCK PHASE = 1)
RM46L450 RM46L850 master_mode_chip_select_phase1_pns160.gifFigure 7-17 SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)

7.11.5 SPI Slave Mode I/O Timings

Table 7-35 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output)(1)(2)(3)(4)

NO. Parameter MIN MAX Unit
1 tc(SPC)S Cycle time, SPICLK(5) 40 ns
2(6) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14 ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14
3(6) tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14 ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14
4(6) td(SPCH-SOMI)S Delay time, SPISOMI valid after SPICLK high (clock polarity = 0) trf(SOMI) + 20 ns
td(SPCL-SOMI)S Delay time, SPISOMI valid after SPICLK low (clock polarity = 1) trf(SOMI) + 20
5(6) th(SPCH-SOMI)S Hold time, SPISOMI data valid after SPICLK high (clock polarity =0) 2 ns
th(SPCL-SOMI)S Hold time, SPISOMI data valid after SPICLK low (clock polarity =1) 2
6(6) tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 4 ns
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 4
7(6) th(SPCL-SIMO)S Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0) 2 ns
th(SPCH-SIMO)S Hold time, SPISIMO data valid after S PICLK high (clock polarity = 1) 2
8 td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn)+ 22 ns
td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+ tr(ENAn) + 22
9 td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn) tc(VCLK)+tf(ENAn)+27 ns
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-7.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
RM46L450 RM46L850 slave_mode_external_timing_phase0_pns160.gifFigure 7-18 SPI Slave Mode External Timing (CLOCK PHASE = 0)
RM46L450 RM46L850 slave_mode_enable_timing_phase0_pns160.gifFigure 7-19 SPI Slave Mode Enable Timing (CLOCK PHASE = 0)

Table 7-36 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output)(1)(2)(3)(4)

NO. Parameter MIN MAX Unit
1 tc(SPC)S Cycle time, SPICLK(5) 40 ns
2(6) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14 ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14
3(6) tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14 ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14
4(6) td(SOMI-SPCL)S Delay time, SPISOMI data valid after SPICLK low (clock polarity = 0) trf(SOMI) + 20 ns
td(SOMI-SPCH)S Delay time, SPISOMI data valid after SPICLK high (clock polarity = 1) trf(SOMI) + 20
5(6) th(SPCL-SOMI)S Hold time, SPISOMI data valid after SPICLK high (clock polarity =0) 2 ns
th(SPCH-SOMI)S Hold time, SPISOMI data valid after SPICLK low (clock polarity =1) 2
6(6) tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 4 ns
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 4
7(6) tv(SPCH-SIMO)S High time, SPISIMO data valid after SPICLK high (clock polarity = 0) 2 ns
tv(SPCL-SIMO)S High time, SPISIMO data valid after SPICLK low (clock polarity = 1) 2
8 td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22 ns
td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22
9 td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn) tc(VCLK)+tf(ENAn)+ 27 ns
10 td(SCSL-SOMI)S Delay time, SOMI valid after SPICSn low (if new data has been written to the SPI buffer) tc(VCLK) 2tc(VCLK)+trf(SOMI)+ 28 ns
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-7.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
RM46L450 RM46L850 slave_mode_external_timing_phase1_pns160.gifFigure 7-20 SPI Slave Mode External Timing (CLOCK PHASE = 1)
RM46L450 RM46L850 slave_mode_enable_timing_phase1_pns160.gifFigure 7-21 SPI Slave Mode Enable Timing (CLOCK PHASE = 1)

7.12 Ethernet Media Access Controller

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the CPU and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QoS) support.

The EMAC controls the flow of packet data from the RM4x device to the PHY. The MDIO module controls PHY configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the RM4x device through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to multiplex and control interrupts.

7.12.1 Ethernet MII Electrical and Timing Specifications

RM46L450 RM46L850 mii_receive_timing_pns160.gifFigure 7-22 MII Receive Timing

Table 7-37 Timing Requirements for EMAC MII Receive

NO. MIN MAX UNIT
1 tsu(MIIRXD - MIIRXCLKH) Setup time, MII_RXD[3:0] before MII_RX_CLK rising edge 8 ns
tsu(MIIRXDV - MIIRXCLKH) Setup time, MII_RX_DV before MII_RX_CLK rising edge 8 ns
tsu(MIIRXER - MIIRXCLKH) Setup time, MII_RX_ER before MII_RX_CLK rising edge 8 ns
2 th(MIIRXCLKH - MIIRXD) Hold time, MII_RXD[3:0] valid after MII_RX_CLK rising edge 8 ns
th(MIIRXCLKH - MIIRXDV) Hold time, MII_RX_DV valid after MII_RX_CLK rising edge 8 ns
th(MIIRXCLKH - MIIRXER) Hold time, MII_RX_ER valid after MII_RX_CLK rising edge 8 ns
RM46L450 RM46L850 mii_transmit_timing_pns160.gifFigure 7-23 MII Transmit Timing

Table 7-38 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit

NO. PARAMETER MIN MAX UNIT
1 td(MIIRXCLKH - MIITXD) Delay time, MII_TX_CLK rising edge to MII_TXD[3:0] valid 5 25 ns
td(MIIRXCLKH - MIITXEN) Delay time, MII_TX_CLK rising edge to MII_TXEN valid 5 25 ns

7.12.2 Ethernet RMII Electrical and Timing Specifications

RM46L450 RM46L850 RMII_Timing_Diagram_spns160.gifFigure 7-24 RMII Timing Diagram

Table 7-39 Timing Requirements for EMAC RMII Receive and RMII_REFCLK

NO. MIN NOM MAX UNIT
1 tc(REFCLK) Cycle time, RMII_REFCLK 20 ns
2 tw(REFCLKH) Pulse width, RMII_REFCLK high 7 13 ns
3 tw(REFCLKL) Pulse width, RMII_REFCLK low 7 13 ns
6 tsu(RXD-REFCLK) Input setup time, RMII_RXD[1:0] valid before RMII_REFCLK high 4 ns
7 th(REFCLK-RXD) Input hold time, RMII_RXD[1:0] valid after RMII_REFCLK high 2 ns
8 tsu(CRSDV-REFCLK) Input setup time, RMII_CRS_DV valid before RMII_REFCLK high 4 ns
9 th(REFCLK-CRSDV) Input hold time, RMII_CRS_DV valid after RMII_REFCLK high 2 ns
10 tsu(RXER-REFCLK) Input setup time, RMII_RX_ER valid before RMII_REFCLK high 4 ns
11 th(REFCLK-RXER) Input hold time, RMII_RX_ER valid after RMII_REFCLK high 2 ns

Table 7-40 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit

NO. PARAMETER MIN MAX UNIT
4 td(REFCLK-TXD) Output delay time, RMII_REFCLK high to RMII_TXD[1:0] valid 2 ns
5 td(REFCLK-TXEN) Output delay time, RMII_REFCLK high to RMII_TXEN valid 2 ns

7.12.3 Management Data Input/Output (MDIO)

RM46L450 RM46L850 MDIO_Input_Timing_spns160.gifFigure 7-25 MDIO Input Timing

Table 7-41 MDIO Input Timing Requirements

NO. Parameter Value Unit
MIN MAX
1 tc(MDCLK) Cycle time, MDCLK 400 - ns
2 tw(MDCLK) Pulse duration, MDCLK high/low 180 - ns
3 tt(MDCLK) Transition time, MDCLK - 5 ns
4 tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK High 33(1) - ns
5 th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK High 10 - ns
(1) This is a discrepancy to IEEE 802.3, but is compatible with many PHY devices.
RM46L450 RM46L850 MDIO_Output_Timing_spns160.gifFigure 7-26 MDIO Output Timing

Table 7-42 MDIO Output Timing Requirements

NO. Parameter Value Unit
MIN MAX
1 tc(MDCLK) Cycle time, MDCLK 400 - ns
7 td(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output valid -7 100 ns

7.13 Universal Serial Bus (USB) Host and Device Controllers

7.13.1 Features

This device provides several varieties of USB functionality, including:

  • One full-speed USB device port compatible with the USB Specification Revision 2.0 and USB Specification Revision 1.1
  • Two USB host ports compatible with USB Specification Revision 2.0, which is based on the OHCI Specification For USB Release 1.0.

7.13.2 Electrical and Timing Specifications

Table 7-43 Full-Speed USB Interface Timing Requirements

NO. Parameter MIN MAX Unit
FSU20 td(VPL, VML) Host time duration, USBx.VP and USBx.VM low together during transition(1) 15 ns
Device time duration, USBx.VP and USBx.VM low together during transition 15 ns
FSU21 td(VPH, VMH) Host time duration, USBx.VP and USBx.VM high together during transition(1) 15 ns
Device time duration, USBx.VP and USBx.VM high together during transition 15 ns
(1) Applies to both host ports, USB1 and USB2

Table 7-44 Full-Speed USB Interface Switching Characteristics(1)

NO. Parameter MIN MAX Unit
FSU15 td(TXENL–TXDATV) Host delay time USBx.TXEN active to USBx.TXDAT valid(2) -2.3 2.1 ns
Device delay time USBx.TXEN active to USBx.TXDAT valid -2.6 0.8 ns
FSU16 td(TXENL–TXSE0V) Host delay time USBx.TXEN active to USBx.TXSE0 valid(2) -2.9 1.8 ns
Device delay time USBx.TXEN active to USBx.TXSE0 valid -1.7 1.0 ns
FSU17 ts(TXDAT–TXSE0) Host skew between USBx.TXDAT and USBx.TXSE0 transition(2) 0 1.7 ns
Device skew between USBx.TXDAT and USBx.TXSE0 transition 0 2.1 ns
FSU18 td(TXENH–TXDATI) Host delay time USBx.TXEN inactive to USBx.TXDAT invalid(2) -2.0 2.2 ns
Device delay time USBx.TXEN inactive to USBx.TXDAT invalid -2.0 0.7 ns
FSU19 td(TXENH–TXSE0I) Host delay time USBx.TXEN inactive to USBx.TXSE0 invalid(2) -2.6 1.9 ns
Device delay time USBx.TXEN inactive to USBx.TXSE0 invalid -1.3 0.9 ns
(1) The capacitive loading is equivalent to 15 pF
(2) Applies to both host ports, USB1 and USB2
RM46L450 RM46L850 usb_modes_newnames_spns160.gifFigure 7-27 Full-Speed USB Interface – Transmit and Receive Modes