The RM41L232 device is a high-performance microcontroller for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and Memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.
The RM41L232 device integrates the ARM Cortex-R4 CPU. The CPU offers an efficient 1.66 DMIPS/MHz, and has configurations that can run up to 80 MHz, providing up to 132 DMIPS. The device operates in little-endian (LE) mode.
The RM41L232 device has 128KB of integrated flash and 32KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (the same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of 80 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes throughout the supported frequency range.
The RM41L232 device features peripherals for real-time control-based applications, including a Next Generation High-End Timer (N2HET) timing coprocessor with up to 19 I/O terminals and a 12-bit Analog-to-Digital Converter (ADC) supporting 16 inputs in the 100-pin package.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a small instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.
The Enhanced Quadrature Encoder Pulse (eQEP) module is used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine as used in high-performance motion and position-control systems.
The device has a 12-bit-resolution MibADC with 16 channels and 64 words of parity-protected buffer RAM. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings. Each sequence can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired.
The device has multiple communication interfaces: one MibSPI, two SPIs, one UART/LIN, and two DCANs. The SPI provides a convenient method of serial high-speed communications between similar shift-register type devices. The UART/LIN supports the Local Interconnect standard 2.1 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial applications) that require reliable serial communication or multiplexed wiring.
The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. The FMPLL provides one of the five possible clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.
The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.
The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is generated or the external nERROR pin is toggled when a fault is detected. The nERROR pin can be monitored externally as an indicator of a fault condition in the microcontroller.
The I/O Multiplexing and Control Module (IOMM) allows the configuration of the input/output pins to support alternate functions. See Table 4-17 for a list of the pins that support multiple functions on this device.
With integrated safety features and a wide choice of communication and control peripherals, the RM41L232 device is an ideal solution for real-time control applications with safety-critical requirements.
Figure 1-1 shows a functional block diagram of the device.
Scope: Applicable updates to the Hercules™ MCU device family, specifically relating to the RM41L232 devices, which are now in the production data (PD) stage of development have been incorporated.
Changes from April 30, 2014 to June 30, 2015 (from Initial Revision (April 2014) to A Revision)
Table 3-1 lists the features of the RM41L232 devices.
FEATURES | DEVICES | |||||||
---|---|---|---|---|---|---|---|---|
Generic Part Number | RM46L852ZWT(1) | RM44L922ZWT | RM44L920PGE | RM44L920PZ | RM44L520PGE | RM44L520PZ | RM42L432PZ(1) | RM41L232PZ |
Package | 337 BGA | 337 BGA | 144 QFP | 100 QFP | 144 QFP | 100 QFP | 100 QFP | 100 QFP |
CPU | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4F | ARM Cortex-R4 | ARM Cortex-R4 |
Frequency (MHz) | 220 | 220 | 200 | 120 | 200 | 120 | 100 | 80 |
Flash (KB) | 1280 | 1024 | 1024 | 1024 | 768 | 768 | 384 | 128 |
RAM (KB) | 192 | 128 | 128 | 128 | 128 | 128 | 32 | 32 |
Data Flash [EEPROM] (KB) | 64 | 64 | 64 | 64 | 64 | 64 | 16 | 16 |
USB OHCI + Device | 2+0 or 1+1 | – | – | – | – | – | – | – |
EMAC | 10/100 | – | – | – | – | – | – | – |
CAN | 3 | 3 | 3 | 2 | 3 | 2 | 2 | 2 |
MibADC 12-bit (Ch) |
2 (24ch) | 2 (24ch) | 2 (24ch) | 2 (24ch) | 2 (24ch) | 2 (16ch) | 1 (16ch) | 1 (16ch) |
N2HET (Ch) | 2 (44) | 2 (44) | 2 (40) | 2 (21) | 2 (40) | 2 (21) | 1 (19) | 1 (19) |
ePWM Channels | 14 | 14 | 14 | 8 | 14 | 8 | – | – |
eCAP Channels | 6 | 6 | 6 | 4 | 6 | 4 | – | – |
eQEP Channels | 2 | 2 | 2 | 1 | 2 | 1 | 1 | 1 |
MibSPI (CS) | 3 (6 + 6 + 4) | 3 (6 + 6 + 4) | 3 (5 + 6 + 1) | 2 (4 + 2) | 3 (5 + 6 + 1) | 2 (4 + 2) | 1 (4) | 1 (4) |
SPI (CS) | 2 (2 + 1) | 2 (2 + 1) | 1 (1) | 1 (1) | 1 (1) | 1 (1) | 2 (4 + 4) | 2 (4 + 4) |
SCI (LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 2 (1 with LIN) | 1(with LIN) | 2 (1 with LIN) | 1(with LIN) | 1(with LIN) | 1(with LIN) |
I2C | 1 | 1 | 1 | – | 1 | – | – | – |
GPIO (INT)(4) | 101 (with 16 interrupt capable) |
101 (with 16 interrupt capable) |
64 (with 16 interrupt capable) |
45 (with 9 interrupt capable) |
64 (with 10 interrupt capable) |
45 (with 9 interrupt capable) |
45 (with 8 interrupt capable) |
45 (with 8 interrupt capable) |
EMIF | 16-bit data | – | – | – | – | – | – | – |
ETM [Trace] (Data) | – | – | – | – | – | – | – | – |
RTP/DMM (Data) | – | – | – | – | – | – | – | – |
Operating Temperature |
–40ºC to 105ºC | –40ºC to 105ºC | –40ºC to 105ºC | –40ºC to 105ºC | –40ºC to 105ºC | –40ºC to 105ºC | –40ºC to 105ºC | –40ºC to 105ºC |
Core Supply (V) | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V | 1.14 V – 1.32 V |
I/O Supply (V) | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V | 3.0 V – 3.6 V |
Figure 4-1 shows the 100-pin PZ QFP package pinout.
Note: Pins can have multiplexed functions. Only the default function is depicted in Figure 4-1.
Table 4-1 through Table 4-16 identify the external signal names, the associated pin numbers along with the mechanical package designator, the pin type (Input, Output, I/O, Power, or Ground), whether the pin has any internal pullup/pulldown, whether the pin can be configured as a GPIO, and a functional pin description.
NOTE
In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to the terminal while nPORRST is low and immediately after nPORRST goes High. The default pull direction may change when software configures the pin for an alternate function. The "Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given terminal by the IOMM control registers.
All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes High. While nPORRST is low, the input buffers are disabled, and the output buffers are disabled with the default pulls enabled.
All output-only signals have the output buffer disabled and the default pull enabled while nPORRST is low, and are configured as outputs with the pulls disabled immediately after nPORRST goes High.
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
N2HET[0] | 19 | I/O | Pulldown | Programmable, 20 µA | Timer input capture or output compare. The N2HET applicable terminals can be programmed as general-purpose input/output (GPIO). Each terminal has a suppression filter with a programmable duration. |
N2HET[2] | 22 | ||||
N2HET[4] | 25 | ||||
N2HET[6] | 26 | ||||
N2HET[8] | 74 | ||||
N2HET[10] | 83 | ||||
N2HET[12] | 89 | ||||
N2HET[14] | 90 | ||||
N2HET[16] | 97 | ||||
MIBSPI1nCS[1]/EQEPS/ N2HET[17] |
93 | ||||
N2HET[18] | 98 | ||||
MIBSPI1nCS[2]/N2HET[20]/ N2HET[19] |
27 | ||||
MIBSPI1nCS[2]/N2HET[20]/ N2HET[19] |
27 | ||||
N2HET[22] | 11 | ||||
N2HET[24] | 64 | ||||
MIBSPI1nCS[3]/N2HET[26] | 39 | ||||
ADEVT/N2HET[28] | 58 | ||||
GIOA[7]/N2HET[29] | 18 | ||||
MIBSPI1nENA/N2HET[23]/ N2HET[30] |
68 | ||||
GIOA[6]/SPI2nCS[1]/N2HET[31] | 12 |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
SPI3CLK/EQEPA | 36 | Input | Pullup | Fixed 20 µA | Enhanced QEP Input A |
SPI3nENA/EQEPB | 37 | Input | Enhanced QEP Input B | ||
SPI3nCS[0]/EQEPI | 38 | I/O | Enhanced QEP Index | ||
MIBSPI1nCS[1]/EQEPS/N2HET[17] | 93 | I/O | Enhanced QEP Strobe |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
GIOA[0]/SPI3nCS[3] | 1 | I/O | Pulldown | Programmable, 20 µA | General-purpose input/output All GPIO terminals can generate interrupts to the CPU on rising/falling/both edges. |
GIOA[1]/SPI3nCS[2] | 2 | ||||
GIOA[2]/SPI3nCS[1] | 5 | ||||
GIOA[3]/SPI2nCS[3] | 8 | ||||
GIOA[4]/SPI2nCS[2] | 9 | ||||
GIOA[5]/EXTCLKIN | 10 | ||||
GIOA[6]/SPI2nCS[1]/N2HET[31] | 12 | ||||
GIOA[7]/N2HET[29] | 18 |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
CAN1RX | 63 | I/O | Pullup | Programmable, 20 µA | CAN1 Receive, or general-purpose I/O (GPIO) |
CAN1TX | 62 | CAN1 Transmit, or GPIO | |||
CAN2RX | 92 | CAN2 Receive, or GPIO | |||
CAN2TX | 91 | CAN2 Transmit, or GPIO |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
MIBSPI1CLK | 67 | I/O | Pullup | Programmable, 20 µA | MibSPI1 Serial Clock, or GPIO |
MIBSPI1nCS[0] | 73 | MibSPI1 Chip Select, or GPIO | |||
MIBSPI1nCS[1]/EQEPS/N2HET[17] | 93 | ||||
MIBSPI1nCS[2]/N2HET[20]/N2HET[19] | 27 | ||||
MIBSPI1nCS[3]/N2HET[26] | 39 | ||||
MIBSPI1nENA/N2HET[23]/N2HET[30] | 68 | MibSPI1 Enable, or GPIO | |||
MIBSPI1SIMO | 65 | MibSPI1 Slave-In-Master-Out, or GPIO | |||
MIBSPI1SOMI | 66 | MibSPI1 Slave-Out-Master-In, or GPIO |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
SPI2CLK | 71 | I/O | Pullup | Programmable, 20 µA | SPI2 Serial Clock, or GPIO |
SPI2nCS[0] | 23 | SPI2 Chip Select, or GPIO | |||
GIOA[6]/SPI2nCS[1]/N2HET[31] | 12 | ||||
GIOA[4]/SPI2nCS[2] | 9 | ||||
GIOA[3]/SPI2nCS[3] | 8 | ||||
SPI2SIMO | 70 | SPI2 Slave-In-Master-Out, or GPIO | |||
SPI2SOMI | 69 | SPI2 Slave-Out-Master-In, or GPIO | |||
The drive strengths for the SPI2CLK, SPI2SIMO, and SPI2SOMI signals are selected individually by configuring the respective SRS bits of the SPIPC9 register fo SPI2. SRS = 0 for 8-mA drive (fast). This is the default mode as the SRS bits in the SPIPC9 register default to 0. SRS = 1 for 2-mA drive (slow) |
|||||
SPI3CLK/EQEPA | 36 | I/O | Pullup | Programmable, 20 µA | SPI3 Serial Clock, or GPIO |
SPI3nCS[0]/EQEPI | 38 | SPI3 Chip Select, or GPIO | |||
GIOA[2]/SPI3nCS[1] | 5 | ||||
GIOA[1]/SPI3nCS[2] | 2 | ||||
GIOA[0]/SPI3nCS[3] | 1 | ||||
SPI3nENA/EQEPB | 37 | SPI3 Enable, or GPIO | |||
SPI3SIMO | 35 | SPI3 Slave-In-Master-Out, or GPIO | |||
SPI3SOMI | 34 | SPI3 Slave-Out-Master-In, or GPIO |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
LINRX | 94 | I/O | Pullup | Programmable, 20 µA | LIN Receive, or GPIO |
LINTX | 95 | LIN Transmit, or GPIO |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
ADEVT/N2HET[28] | 58 | I/O | Pullup | Programmable, 20 µA | ADC event trigger or GPIO |
ADIN[0] | 42 | Input | N/A | None | Analog inputs |
ADIN[1] | 49 | ||||
ADIN[2] | 51 | ||||
ADIN[3] | 52 | ||||
ADIN[4] | 54 | ||||
ADIN[5] | 55 | ||||
ADIN[6] | 56 | ||||
ADIN[7] | 43 | ||||
ADIN[8] | 57 | ||||
ADIN[9] | 48 | ||||
ADIN[10] | 50 | ||||
ADIN[11] | 53 | ||||
ADIN[16] | 40 | ||||
ADIN[17] | 41 | ||||
ADIN[20] | 44 | ||||
ADIN[21] | 45 | ||||
VCCAD/ADREFHI | 46 | Input/Power | N/A | None | ADC high reference level/ADC operating supply |
VSSAD/ADREFLO | 47 | Input/Ground | N/A | None | ADC low reference level/ADC supply ground |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
ECLK | 84 | I/O | Pulldown | Programmable, 20 µA | External prescaled clock output, or GPIO. |
GIOA[5]/EXTCLKIN | 10 | Input | Pulldown | 20 µA | External Clock In |
nPORRST | 31 | Input | Pulldown | 100 µA | Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. |
nRST | 81 | I/O | Pullup | 100 µA | The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter. |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
nERROR | 82 | I/O | Pulldown | 20 µA | ESM error signal. Indicates error of high severity. |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
OSCIN | 14 | Input | N/A | None | From external crystal/resonator, or external clock input |
OSCOUT | 16 | Output | N/A | None | To external crystal/resonator |
KELVIN_GND | 15 | Input | N/A | None | Dedicated ground for oscillator |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
nTRST | 76 | Input | Pulldown | Fixed, 100 µA | JTAG test hardware reset |
RTCK | 80 | Output | N/A | None | JTAG return test clock |
TCK | 79 | Input | Pulldown | Fixed, 100 µA | JTAG test clock |
TDI | 77 | I/O | Pullup | Fixed, 100 µA | JTAG test data in |
TDO | 78 | Output | Fixed, 100-µA Pulldown | None | JTAG test data out |
TMS | 75 | I/O | Pullup | Fixed, 100 µA | JTAG test select |
TEST | 24 | I/O | Pulldown | Fixed, 100 µA | Test enable. This terminal must be connected to ground directly or through a pulldown resistor. |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
FLTP1 | 3 | Input | N/A | None | Flash test pins. For proper operation this terminal must connect only to a test pad or not be connected at all [no connect (NC)]. The test pad must not be exposed in the final product where it might be subjected to an ESD event. |
FLTP2 | 4 | Input | N/A | None | |
VCCP | 96 | 3.3-V Power | N/A | None | Flash external pump voltage (3.3 V). This terminal is required for both flash read and flash program and erase operations. |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
VCC | 13 | 1.2-V Power | N/A | None | Digital logic and RAM supply |
VCC | 21 | ||||
VCC | 30 | ||||
VCC | 32 | ||||
VCC | 61 | ||||
VCC | 88 | ||||
VCC | 99 |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
VCCIO | 6 | 3.3-V Power | N/A | None | I/O supply |
VCCIO | 28 | ||||
VCCIO | 60 | ||||
VCCIO | 85 |
TERMINAL | SIGNAL TYPE | RESET PULL STATE | PULL TYPE | DESCRIPTION | |
---|---|---|---|---|---|
SIGNAL NAME | 100 PZ | ||||
VSS | 7 | Ground | N/A | None | Device Ground Reference. This is a single ground reference for all supplies except for the ADC supply. |
VSS | 17 | ||||
VSS | 20 | ||||
VSS | 29 | ||||
VSS | 33 | ||||
VSS | 59 | ||||
VSS | 72 | ||||
VSS | 86 | ||||
VSS | 87 | ||||
VSS | 100 |
Output multiplexing will be used in the device. The multiplexing is used to allow development of additional package and feature combinations as well as to maintain pinout compatibility with the marketing device family.
In all cases indicated as multiplexed, the output buffers are multiplexed.
Table 4-17 shows the output signal multiplexing and control signals for selecting the desired functionality for each pin.
For example, consider the multiplexing on pin 18, shown in Table 4-18 .
100 PZ PIN | DEFAULT FUNCTION |
CONTROL 1 | OPTION2 | CONTROL 2 | OPTION 3 | CONTROL 3 |
---|---|---|---|---|---|---|
1 | GIOA[0] | PINMMR0[8] | SPI3nCS[3] | PINMMR0[9] | – | – |
2 | GIOA[1] | PINMMR1[0] | SPI3nCS[2] | PINMMR1[1] | – | – |
5 | GIOA[2] | PINMMR1[8] | SPI3nCS[1] | PINMMR1[9] | – | – |
8 | GIOA[3] | PINMMR1[16] | SPI2nCS[3] | PINMMR1[17] | – | – |
9 | GIOA[4] | PINMMR1[24] | SPI2nCS[2] | PINMMR1[25] | – | – |
10 | GIOA[5] | PINMMR2[0] | EXTCLKIN | PINMMR2[1] | – | – |
12 | GIOA[6] | PINMMR2[8] | SPI2nCS[1] | PINMMR2[9] | N2HET[31] | PINMMR2[10] |
18 | GIOA[7] | PINMMR2[16] | N2HET[29] | PINMMR2[17] | – | – |
93 | MIBSPI1nCS[1] | PINMMR6[8] | EQEPS | PINMMR6[9] | N2HET[17] | PINMMR6[10] |
27 | MIBSPI1nCS[2] | PINMMR3[0] | N2HET[20] | PINMMR3[1] | N2HET[19] | PINMMR3[2] |
39 | MIBSPI1nCS[3] | PINMMR4[8] | N2HET[26] | PINMMR4[9] | – | – |
68 | MIBSPI1nENA | PINMMR5[8] | N2HET[23] | PINMMR5[9] | N2HET[30] | PINMMR5[10] |
36 | SPI3CLK | PINMMR3[16] | EQEPA | PINMMR3[17] | – | – |
38 | SPI3nCS[0] | PINMMR4[0] | EQEPI | PINMMR4[1] | – | – |
37 | SPI3nENA | PINMMR3[24] | EQEPB | PINMMR3[25] | – | – |
58 | ADEVT | PINMMR4[16] | N2HET[28] | PINMMR4[17] | – | – |
100 PZ PIN | DEFAULT FUNCTION |
CONTROL 1 | OPTION2 | CONTROL 2 | OPTION 3 | CONTROL 3 |
---|---|---|---|---|---|---|
18 | GIOA[7] | PINMMR2[16] | N2HET[29] | PINMMR2[17] | – | – |
Special controls are implemented to affect particular functions on this microcontroller. These controls are described in this section.