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The parallel pursuit of cost reduction and miniaturization in recent years has increased emphasis on very small integrated circuit (IC) package solutions. This is particularly evident in consumer-based end equipment using digital signal processor (DSP) solutions such as wireless telephones, laptop computers, and hard-disk drives. Despite the formal definition, packages with an area similar in size to the IC they encapsulate are loosely referred to as chip scale packages (CSPs). Figure 1-1 illustrates this trend.
CSPs are in many ways an ideal solution to the cost reduction and miniaturization requirements. They offer enormous area reductions compared to quad flat packages (QFPs) and have increasing potential to do so without adding to system-level cost. In the best case, CSPs compete today on a cost-per-terminal basis with QFPs. Various CSPs from Texas Instruments (TI) are now available at cost parity with thin QFPs.
Texas Instruments produces a laminate-based family of CSPs known as New Fine Pitch Ball Grid Array packages (also referred to as nFBGA packages). Like most other CSPs, nFBGA packages use solder alloy balls as the interconnect between the package substrate and the board on which the package is soldered. The nFBGA family comes in a range of solder ball pitch, and can accommodate various stacked die configurations, with as many as three die housed in each package. Figure 1-2 shows the structure of TI’s nFBGA package.
TI also offers small body nFBGAs for customers looking to reduce the PCB footprint even further. Structure is nearly identical to that of the standard nFBGA shown in Figure 1-2. The major difference is the package thickness. Standard nFBGAs have a thickness of ~1 mm while the small body variants can range from 0.45-1 mm. This is achieved by using a thinner substrate material and die attach film instead of epoxy.
Package stack up can be minimized even further by using solder bumps rather than the standard BGA solder balls. The reduced height of the bumps allows the smallest possible package height while offering exceptional board level reliability performance. Figure 1-3 shows the structure of TI’s small body nFBGAs.
Texas Instruments addressed several key issues in package assembly to produce a CSP that is not only physically and mechanically stable but cost-effective for a wide variety of applications.
Figure 1-4 shows a general flow used to produce TI nFBGA packages.
The nFBGA package has been fully qualified in numerous applications and is being used extensively in mobile phones, laptops, modems, handheld devices, and office environment equipment. For more information on using reliable and cost-effective nFBGA packaging in your application, contact your local TI field sales office.
Designs of both the nFBGA package itself and the printed circuit board (PCB) are important in achieving good manufacturability and optimum reliability. In particular, the diameters of the package vias and the board lands are critical. While the actual sizes of these dimensions are important, their ratio is more critical. Figure 2-1 illustrates the package via-to-PCB configuration and Figure 2-2 illustrates why this ratio is critical.
In the top view of Figure 2-2, the package via is larger than the PCB via, and the solder ball is prone to crack prematurely at the PCB interface. In the middle view, the PCB via is larger than the package via, which leads to cracks at the package surface. In the bottom view, where the ratio is almost 1:1, the stresses are equalized and neither site is more susceptible to cracking than the other.
Solder lands on the PCB are generally simple round pads. Solder lands are either solder-mask-defined or non-solder-mask-defined.
For an example of optimum land diameters and configurations for a common nFBGA pitch, see Table 2-1.
All Measurements in mm | Ball Size, SMO, Pad Size and Apertures are Shown in Diameters | |||||
---|---|---|---|---|---|---|
Ball Pitch | Solder Mask Type | PCB Design | Stencil Design | Area Aspect Ratio | ||
SMO | Pad Size | Thickness | Aperture | |||
0.4 | SMD | 0.225 | 0.300 | 0.076 | 0.250 | 0.82 |
NSMD | 0.300 | 0.225 | ||||
0.5 | SMD | 0.300 | 0.400 | 0.100 | 0.300 | 0.75 |
NSMD | 0.400 | 0.300 | ||||
0.65 | SMD | 0.350 | 0.450 | 0.127 | 0.350 | 0.69 |
NSMD | 0.450 | 0.350 | ||||
0.8 | SMD | 0.400 | 0.500 | 0.152 | 0.400 | 0.66 |
NSMD | 0.500 | 0.400 | ||||
1 | SMD | 0.450 | 0.550 | 0.152 | 0.450 | 0.74 |
NSMD | 0.550 | 0.450 |
Figure 2-4 presents some design considerations based on commonly used PCB design rules. Conventionally, the pads are connected by wide copper traces to other devices or to plated through holes (PTH). As a rule, the mounting pads must be isolated from the PTH. Placing the PTH interstitially to the land pads often achieves this.
A challenge when designing with CSP packages is that as available space contracts, the space available for signal fanout also decreases. Routing of nFBGA packages can be especially challenging because of the tight ball pitch and a full array of solder balls that most packages have. By using a few high-density routing techniques, the PCB designer can minimize many of these design and manufacturing challenges.