SPRAAV1C May   2009  – March 2020 AM3703 , AM3715 , OMAP3503 , OMAP3515 , OMAP3525 , OMAP3530

 

  1.   PCB Design Guidelines for 0.4mm Package-On-Package (PoP) Packages, Part I
    1.     Trademarks
    2. 1  Using This Guide
    3. 2  A Word of Caution
    4. 3  A Team Sport
    5. 4  Be Wary of Quotes
    6. 5  Don’t Forget Your CAD Tools
    7. 6  Metric Vs English
    8. 7  PCB Fab Limits
    9. 8  Routing and Layer Stackup
    10. 9  OMAP35x 0.4mm Pitch
    11. 10 Pad Type
    12. 11 PCB Pad Dimensions for 0.4mm BGA Package
    13. 12 Multiple BGA Packages
    14. 13 Etch Traps and Heat Sinks
    15. 14 Vias and VIP
    16. 15 Laser Blind Vias
    17. 16 Filled Vias
    18. 17 Know Your Tools
    19. 18 BeagleBoard
    20. 19 BeagleBoard Views
      1. 19.1 Top Layer – Signal - Area Underneath the OMAP35x
      2. 19.2 Layer 2 – Ground
      3. 19.3 Layer 3 – Signal
      4. 19.4 Layer 4 – Signal
      5. 19.5 Layer 5 – Power (VDD2)
      6. 19.6 Layer 6 – Signal – Bottom Copper – Bottom Component Outlines
    21. 20 OMAP35x Decoupling
    22. 21 PCB Finishes for High Density Interconnect (HDI)
    23. 22 Real World Second Opinion
    24. 23 Acknowledgments
    25. 24 References
  2.   Revision History

24 References

  • Printed Circuits Handbook - 6th Edition, Clyde Coombs, Jr., McGraw-Hill, January 2008
  • PCB Design and SMT Assembly/Rework Guidelines for MCM-L Packages, 2001–2006, Skyworks Solutions, Inc. All Rights Reserved.
  • Semicondutor Device Mount Manual, http://www.necel.com/pkg/en/mount/
  • Texas Instruments: PCB Assembly Guidelines for 0.4mm Package-On-Package (PoP) Packages, Part II
  • PC-Board Layout Techniques for ML67Q4060/4061 ARM 7 W-CSP Packaged Devices, October 5, 2005, Rev 1.0, OKI Semiconductor
  • PCB Pad Pattern Design and Surface-Mount Considerations, XAPP439 (v1.0), April 11, 2005, Xilinix
  • Eliminating Microvoid Risk Via An Optimized Surface Finish Process, Donald Cullen, Witold Paw, John Swanson, Lenora Toscano, MacDermid, Inc. Waterbury, CT USA
  • Effect Of Printed Wiring Board Warpage On Ball Grid Arrays Over Temperature, Kyra Ewer and Jeffrey Seekatz Raytheon, Dallas, TX. 2004
  • Design Method for High Reliable Flip Chip BGA Package, Naoto Saito, Hitachi Ltd. 2001
  • How to Control Voiding in Reflow Soldering, Dr. Ning-Cheng Lee, Indium, 2006
  • Reflow Soldering Processing and Troubleshooting SMT, BGA, CSP, and Flip-Chip Technologies, Newnes, pp. 288, 2001
  • Voiding of Lead-Free Soldering at Microvia, Dr. Ning-Cheng Lee, Indium, 2001
  • The Effect Of Via-In-Pad Via-Fill On Solder Joint Void Formation, Adam Singer, Cookson Electronics Foxboro, MA, 2002
  • Impact Of Microvia-In-Pad Design On Void Formation, Frank Grano, Sanmina-Sci, 2001
  • Voids in Solder Joints, Raiyo Aspandiar, Intel, 2005
  • Package-on-Package (PoP) Stacking and Board Level Reliability, Results of Joint Industry Study, Lee Smith - Amkor Technology, 2005
  • Surface Mount Requirements for Land Grid Array (LGA) Packages, Amkor Technology, Inc 2002
  • A Study on Package Stacking Process for Package-on-Package (PoP), Akito Yoshida, et. al, Sharp, Senju, Panasonic, Amkor
  • 0.4mm BGA Fabrication Result Based Design Requirements, Shrikant Patel, Eagle Circuits 2006
  • Package-on-Package JEDEC Standard No. 21-C, release 16
  • NAND Flash and Mobile DDR SDRAM, 1Gb NAND Flash and 512Mb Mobile DDR SDRAM Combination Memory Part-on-Part (PoP), Micron Datasheet
  • Flip Chip CSP Packages, Application Note On Semiconductor, 2003
  • Surface Mounting Technology BGA Assembly Guidelines, AN-3011 Fairchild, 2001
  • Stencil Design Guidelines, www.alphametals.com/products/stencils
  • PCB Layout Recommendations for BGA Packages, TN1074, Lattice Semiconductor, 2006
  • Stacked Package-on-Package (PoP) Design Guidelines, Moody Dreiza, Amkor, 2004
  • NanoStar_ & NanoFree_ 300_m Solder Bump Wafer Chip-Scale Package Application, SBVA017 Rosson, TI, 2004
  • Solder Stencil Design Guidelines, Cookson Electronics at www.alphametals.com 2006
  • Design for Manufacturability of Rigid Multi-Layer Boards, Hausherr, PCB Libraries 2006
  • Stencil Design Guidelines, Coleman Photo Stencil, 2000
  • Board Routability Guidelines with Xilinx Fine-Pitch BGA Packages, Maheshwari, XAPP157, 2002
  • Texas Instruments: MicroStar BGA™ Packaging Reference Guide
  • Substrate Topics, Rob Rowland, RadiSys Corporation, SMTA International 2003

    • EMI Resources and References

  • Ott, H. W., Noise Reduction Techniques in Electronic Systems, Second Edition, Wiley Interscience, 1988.
  • Johnson, H. W. & Graham, M., High-Speed Digital Design, Prentice-Hall, 1993.
  • Montrose, M. I., Printed Circuit Board Design Techniques for EMC Compliance, IEEE Press, 1996.
  • Fitts, M., The Truth About Microvias, Printed Circuit Design, February 2000.
  • Edwards, T. C., Foundations of Microstrip Circuit Design, Second Edition, John Wiley & Sons, 1992.
  • IPC-D-317A, Design Guidelines for Electronic Packaging Utilizing High Speed Techniques, 1995.
  • Wadell, B. C., Transmission Line Design Handbook, Artech House, 1991.
  • Johnson, H., Why Digital Engineers Don’t Believe in EMC, IEEE EMC Society Newsletter, Spring, 1998.
  • Lau, J. H., Ball Grid Array Technology, McGraw-Hill, 1995. IEEE EMC Society web page at www.emcs.org.
  • Henry Ott Consultants web page at www.hottconsultants.com.

    • Other Useful PCB Design Guidelines

  • Design for Manufacturability of Rigid Multi-Layer Boards, Tom Hausherr; PCB Libraries, Inc., Des Plaines, IL; www.pcblibraries.com.