SPRAB89A September 2011 – March 2014
The C6000 has at least 32 general-purpose 32-bit registers. Registers may contain integers, floating-point values, or pointers. The general purpose registers are divided into two register files, designated as A and B.
B15 is designated as the Stack Pointer (SP). The stack pointer must always remain aligned on a 2-word (8 byte) boundary. The SP points at the first aligned address below (less than) the currently allocated stack (see Section 4.4).
B14 is designated as the Data Page Pointer (DP). It points to the beginning of the data segment for the currently active object.
The ABI does not designate a dedicated Frame Pointer (FP) register. However, the TI compiler uses A15 as a frame pointer in some circumstances.
GCC supports lexically nested functions as a language extension. The implementation uses a register, called the static chain register, to provide the parent function's activation context to the child. The choice of register is largely toolchain-specific, unless the call is interceded in some way (by a trampoline, for example). For this reason, the ABI designates A2 as the recommended choice for the static chain register. The calling conventions support this designation by including A2 as one the registers involved in function linkage, requiring its value to be preserved between a call site and the entry point of the callee.
The ABI designates A10-A15 and B10-B15 as callee-saved registers. That is, a called function is expected to preserve them so they have the same value on return from a function as they had at the point of the call. Note that this set includes the SP (B15) and DP (B14).
In addition, the ILC and RILC are callee-saved registers. These are control registers used by the C64+'s SPLOOP mechanism.
All other registers are caller-save registers. That is, they are not preserved across a call, so if their value is needed following the call, the caller is responsible for saving and restoring their contents.
The Address Mode Register (AMR) is a user-writable control register that enables circular addressing. At function call boundaries bits 0-15 of the AMR must be 0 so that circular addressing is disabled.
Table 3-1 lists the registers and their role in the ABI.
Register | Alias | Preserved by Callee | Role in Calling Convention |
---|---|---|---|
A0 | no | ||
A1 | no | ||
A2 | no | Static chain register for nested functions | |
A3 | no | Address for returned-by-reference structure | |
A4 | no | First argument; return value (LSW) | |
A5 | no | First argument; return value (MSW) | |
A6 | no | Third argument (LSW) | |
A7 | no | Third argument (MSW) | |
A8 | no | Fifth argument (LSW) | |
A9 | no | Fifth argument (MSW) | |
A10 | yes | Seventh argument (LSW) | |
A11 | yes | Seventh argument (MSW) | |
A12 | yes | Ninth argument (LSW) | |
A13 | yes | Ninth argument (MSW) | |
A14 | yes | ||
A15 | FP | yes | Frame pointer |
A16-A31 | no | ||
B0 | no | Dynamic reloc offset argument to lazy binder; see Section 15.7 | |
B1 | no | Dynamic reloc offset argument to lazy binder; see Section 15.7 | |
B2 | no | ||
B3 | no | Return address | |
B4 | no | Second argument (LSW) | |
B5 | no | Second argument (MSW) | |
B6 | no | Fourth argument (LSW) | |
B7 | no | Fourth argument (MSW) | |
B8 | no | Sixth argument (LSW) | |
B9 | no | Sixth argument (MSW) | |
B10 | yes | Eighth argument (LSW) | |
B11 | yes | Eighth argument (MSW) | |
B12 | yes | Tenth argument (LSW) | |
B13 | yes | Tenth argument (MSW) | |
B14 | DP | yes | Data page pointer |
B15 | SP | yes | Stack pointer |
B16-B29 | no | ||
B30-B31 | no! | Trampoline scratch registers; see Section 3.8 |