SPRABA5D January 2014 – January 2019 AM1802 , AM1802 , AM1806 , AM1806 , AM1808 , AM1808 , AM1810 , AM1810
The PLL0 Configuration function configures the PLL0 registers. This function takes two arguments, as shown below.
The PLL0 configuration register is shown in Figure 29 and described in Table 17.
31 | 24 | 23 | 16 | 15 | 8 | 7 | 0 |
Arg1 | CLKMODE | PLLM | PREDIV | POSTDIV | ||||||||||||||||||||||||||||
Arg2 | Reserved | PLLDIV1 | PLLDIV3 | PLLDIV7 |
Bit | Field | Value | Description | |
---|---|---|---|---|
Arg1 | 31-24 | CLKMODE | Value to be programmed to the PLL clock source. | |
0 | Crystal | |||
1 | Oscillator | |||
23-16 | PLLM | Value to be programmed to the PLL multiplier register. | ||
15-8 | PLLDIV | Value to be programmed to the PLL PREDIV register, used to divide the input clock before the PLL multiplier. | ||
7-0 | POSTDIV | Value to be programmed to the PLL POSTDIV register, used to divide the output of the the PLL multiplier. | ||
Arg2 | 31-24 | Reserved | 0 | Reserved |
23-0 | PLLDIV1
PLLDIV3 PLLDIV7 |
Values to be programmed to the PLLDIV1, PLLDIV3 and PLLDIV7 registers, used to generate SYSCLK1, SYSCLK2, SYSCLK4, SYSCLK6, SYSCLK3, and SYSCLK7.
SYSCLK6 = SYSCLK1, SYSCLK2 = SYSCLK1/2, SYSCLK4 = SYSCLK1/4 |