SPRABA5D January 2014 – January 2019 AM1802 , AM1802 , AM1806 , AM1806 , AM1808 , AM1808 , AM1810 , AM1810
The SPI master register is shown in Figure 31 and described in Table 19.
31 | 8 | 7 | 0 |
Arg1 | Reserved | PRESCALE |
Bit | Field | Value | Description |
---|---|---|---|
31-8 | Reserved | 0 | Reserved |
7-0 | PRESCALE | Value to be programmed to the PRESCALE field of the SPIFMT register |