SPRABI1D January   2018  – July 2022 66AK2E05 , 66AK2G12 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Background
  4. 3 Migrating Designs From DDR2 to DDR3 (Features and Comparisons)
    1. 3.1 Topologies
      1. 3.1.1 Balanced Line Topology
        1. 3.1.1.1 Balanced Line Topology Issues
      2. 3.1.2 Fly-By Topology
        1. 3.1.2.1 Balanced Line Topology Issues
    2. 3.2 ECC (Error Correction)
    3. 3.3 DDR3 Features and Improvements
      1. 3.3.1 Read Leveling
      2. 3.3.2 Write Leveling
      3. 3.3.3 Pre-fetch
      4. 3.3.4 ZQ Calibration
      5. 3.3.5 Reset Pin Functionality
      6. 3.3.6 Additional DDR2 to DDR3 Differences
  5. 4 Prerequisites
    1. 4.1 High Speed Designs
    2. 4.2 JEDEC DDR3 Specification – Compatibility and Familiarity
    3. 4.3 Memory Types
    4. 4.4 Memory Speeds
    5. 4.5 Addressable Memory Space
    6. 4.6 DDR3 SDRAM/UDIMM Memories, Topologies, and Configurations
      1. 4.6.1 Topologies
      2. 4.6.2 Configurations
        1. 4.6.2.1 Memories – SDRAM Selection Criteria
    7. 4.7 DRAM Electrical Interface Requirements
      1. 4.7.1 Slew
      2. 4.7.2 Overshoot and Undershoot Specifications
        1. 4.7.2.1 Overshoot and Undershoot Example Calculations
      3. 4.7.3 Typical DDR3 AC and DC Characteristics
      4. 4.7.4 DDR3 Tolerances and Noise – Reference Signals
  6. 5 Package Selection
    1. 5.1 Summary
      1. 5.1.1 ×4 SDRAM
      2. 5.1.2 ×8 SDRAM
      3. 5.1.3 ×16 SDRAM
      4. 5.1.4 ×32 SDRAM
      5. 5.1.5 ×64 SDRAM
  7. 6 Physical Design and Implementation
    1. 6.1 Electrical Connections
      1. 6.1.1 Pin Connectivity and Unused Pins – SDRAM Examples
      2. 6.1.2 Pin Connectivity – ECC UDIMM and Non-ECC UDIMM Examples
    2. 6.2 Signal Terminations
      1. 6.2.1 External Terminations – When Using Read and Write Leveling
      2. 6.2.2 External Terminations – When Read and Write Leveling is Not Used
      3. 6.2.3 Internal Termination – On-Die Terminations
      4. 6.2.4 Active Terminations
      5. 6.2.5 Passive Terminations
      6. 6.2.6 Termination Component Selection
    3. 6.3 Mechanical Layout and Routing Considerations
      1. 6.3.1 Routing Considerations – SDRAMs
        1. 6.3.1.1  Mechanical Layout – SDRAMs
        2. 6.3.1.2  Stack Up – SDRAMs
        3. 6.3.1.3  Routing Rules – General Overview (SDRAMs)
        4. 6.3.1.4  Routing Rules – Address and Command Lines (SDRAMs)
        5. 6.3.1.5  Routing Rules – Control Lines (SDRAMs)
        6. 6.3.1.6  Routing Rules – Data Lines (SDRAMs)
        7. 6.3.1.7  Routing Rules – Clock Lines (SDRAMs)
        8. 6.3.1.8  Routing Rules – Power (SDRAMs)
        9. 6.3.1.9  Write Leveling Limit Impact on Routing – KeyStone I
        10. 6.3.1.10 Round-Trip Delay Impact on Routing – KeyStone I
        11. 6.3.1.11 Write Leveling Limit Impact on Routing – KeyStone II
        12. 6.3.1.12 Round-Trip Delay Impact on Routing – KeyStone II
      2. 6.3.2 Routing Considerations – UDIMMs
        1. 6.3.2.1 Mechanical Layout – UDIMMs
        2. 6.3.2.2 Stack Up – UDIMMs
        3. 6.3.2.3 Routing Rules – General Overview (UDIMMs)
        4. 6.3.2.4 Routing Rules – Address and Command Lines (UDIMMs)
        5. 6.3.2.5 Routing Rules – Control Lines (UDIMMs)
        6. 6.3.2.6 Routing Rules – Data Lines (UDIMMs)
        7. 6.3.2.7 Routing Rules – Clock Lines (UDIMMs)
        8. 6.3.2.8 Routing Rules – Power (UDIMMs)
        9. 6.3.2.9 Write-Leveling Limit Impact on Routing
    4. 6.4 Timing Considerations
    5. 6.5 Impedance Considerations
      1. 6.5.1 Routing Impedances – KeyStone I Devices
        1. 6.5.1.1 Data Group Signals
        2. 6.5.1.2 Fly-By Signals
      2. 6.5.2 Routing Impedances – KeyStone II Devices
        1. 6.5.2.1 Data Group Signals
        2. 6.5.2.2 Fly-By Signals
      3. 6.5.3 Comparison to JEDEC UDIMM Impedance Recommendations
    6. 6.6 Switching and Output Considerations
  8. 7 Simulation and Modeling
    1. 7.1 Simulation and Modeling
    2. 7.2 Tools
    3. 7.3 Models
    4. 7.4 TI Commitment
  9. 8 Power
    1. 8.1 DDR3 SDRAM Power Requirements
      1. 8.1.1 Vref Voltage Requirements
      2. 8.1.2 VTT Voltage Requirements
    2. 8.2 DSP DDR3 Power Requirements
    3. 8.3 DDR3 Power Estimation
    4. 8.4 DSP DDR3 Interface Power Estimation
    5. 8.5 Sequencing – DDR3 and DSP
  10. 9 Disclaimers
  11. 10References
  12. 11Revision History

4.6.2 Configurations

The current DDR3 controller design implementation allows multiple DRAM configurations to be used. The following list describes the known usable

DRAM configurations compatible with TI KeyStone family of DSPs. For a definitive confirmation on usable memory configurations and bus widths before proceeding, see the device-specific data manual.

Table 4-1through Table 4-4 are intended to provide a general overview of the possible DDR3 DRAM topologies usable with the KeyStone DSP. In all cases, only JEDEC-compliant (JESD79-3C) SDRAMs are supported. For all of the tables below, the notation * implies possible support, not a plan of record.

Table 4-1 ×8 Width DDR3 SDRAM Possible Configurations Supported
Device Width Total Memory / Memory Topology Rank Width Total Size
×8 SDRAM 1Gb / (16M × 8 × 8) × 2 SDRAMs ×16 256MB
1Gb / (16M × 8 × 8) × 4 SDRAMs ×32 512MB
1Gb / (16M × 8 × 8) × 8 SDRAMs ×64 1024MB
1Gb / (16M × 8 × 8) × 8 SDRAMs × 2 ranks ×64 2048MB
2Gb / (32M × 8 × 8) × 2 SDRAMs ×16 512MB
2Gb / (32M × 8 × 8) × 4 SDRAMs ×32 1024MB
2Gb / (32M × 8 × 8) × 8 SDRAMs ×64 2048MB
2Gb / (32M × 8 × 8) × 8 SDRAMs × 2 ranks ×64 4096MB
4Gb / (64M × 8 × 8) × 2 SDRAMs ×16 1024MB
4Gb / (64M × 8 × 8) × 4 SDRAMs ×32 2048MB
4Gb / (64M × 8 × 8) × 8 SDRAMs ×64 4096MB
4Gb / (64M × 8 × 8) × 8 SDRAMs × 2 ranks ×64 8192MB
8Gb / (128M × 8 × 8) × 2 SDRAMs ×16 2048MB
8Gb / (128M × 8 × 8) × 4 SDRAMs ×32 4096MB
8Gb / (128M × 8 × 8) × 8 SDRAMs ×64 8192MB
Table 4-2 ×16 Width DDR3 SDRAM Possible Configurations Supported
Device Width Total Memory / Memory Topology Rank Width Total Size
×16 SDRAM 1Gb / (8M × 16 × 8) × 1 SDRAMs ×16 128MB
1Gb / (8M × 16 × 8) × 2 SDRAMs ×32 256MB
1Gb / (8M × 16 × 8) × 4 SDRAMs ×64 512MB
1Gb / (8M × 16 × 8) × 4 SDRAMs × 2 ranks ×64 1024MB
2Gb / (16M × 16 × 8) × 1 SDRAM ×16 256MB
2Gb / (16M × 16 × 8) × 2 SDRAMs ×32 512MB
2Gb / (16M × 16 × 8) × 4 SDRAMs ×64 1024MB
2Gb / (16M × 16 × 8) × 4 SDRAMs × 2 ranks ×64 2048MB
4Gb / (32M × 16 × 8) × 1 SDRAMs ×16 512MB
4Gb / (32M × 16 × 8) × 2 SDRAMs ×32 1024MB
4Gb / (32M × 16 × 8) × 4 SDRAMs ×64 2048MB
4Gb / (32M × 16 × 8) × 4 SDRAMs × 2 ranks ×64 4096MB
8Gb / (64M × 16 × 8) × 1 SDRAMs ×16 1024MB
8Gb / (64M × 16 × 8) × 2 SDRAMs ×32 2048MB
8Gb / (64M × 16 × 8) × 4 SDRAMs ×64 4096MB
8Gb / (64M × 16 × 8) × 4 SDRAMs × 2 ranks ×64 8192MB
Table 4-3 ×32 Width DDR3 SDRAM Possible Configurations Supported
Device Width Total Memory / Memory Topology Rank Width Total Size
×32 SDRAM 2Gb / (8M × 32 ×8) × 1 SDRAM ×32 256MB*
2Gb / (8M × 32 × 8) × 2 SDRAMs ×64 512MB*
2Gb / (8M × 32 × 8) × 1 SDRAM × 2 ranks ×32 512MB*
2Gb / (8M × 32 × 8) × 2 SDRAMs × 2 ranks ×64 1024MB*
4Gb / (16M × 32 × 8) × 1 SDRAM ×32 512MB*
4Gb / (16M × 32 × 8) × 2 SDRAM ×64 1024MB*
4Gb / (16M × 32 × 8) × 1 SDRAM × 2 ranks ×32 1024MB*
4Gb / (16M × 32 × 8) × 2 SDRAMs × 2 ranks ×64 2048MB*

In addition to the discrete SDRAM devices configurations listed above, the following ECC configurations are supported.

Table 4-4 Discrete SDRAM Configurations With ECC
Device Width Memory Rank Topology Rank Width Total Size
×8 SDRAM 1Gb (16M × 8 × 8) × 5 SDRAMs ×36 512MB
1Gb (16M × 8 × 8) × 9 SDRAMs ×72 1024MB
1Gb (16M × 8 × 8) × 9 SDRAMs × 2 ranks ×72 2048MB
2Gb (32M × 8 × 8) × 5 SDRAMs ×36 1024MB
2Gb (32M × 8 × 8) × 9 SDRAMs ×72 2048MB
2Gb (32M × 8 × 8) × 9 SDRAMs × 2 ranks ×72 4096MB
4Gb (64M × 8 × 8) × 5 SDRAMs ×36 2048MB
4Gb (64M × 8 × 8) × 9 SDRAMs ×72 4096MB
4Gb (64M × 8 × 8) × 9 SDRAMs × 2 ranks ×72 8192MB
8Gb (64M × 8 × 8) × 5 SDRAMs ×36 4096MB
8Gb (64M × 8 × 8) × 9 SDRAMs ×72 8192MB
×16 SDRAM (1) 1Gb (8M × 16 × 8) × 3 SDRAMs ×36 256MB
1Gb (8M × 16 × 8) × 5 SDRAMs ×72 512MB
1Gb (8M × 16 × 8) × 5 SDRAMs × 2 ranks ×72 1024MB
2Gb (16M × 16 × 8) × 3 SDRAMs ×36 512MB
2Gb (16M × 16 × 8) × 5 SDRAMs ×72 1024MB
2Gb (16M × 16 × 8) × 5 SDRAMs × 2 ranks ×72 2048MB
4Gb (32M × 16 × 8) × 3 SDRAMs ×36 1024MB
4Gb (32M × 16 × 8) × 5 SDRAMs ×72 2048MB
4Gb (32M × 16 × 8) × 5 SDRAMs × 2 ranks ×72 4096MB
8Gb (64M × 16 × 8) × 3 SDRAMs ×36 2048MB
8Gb (64M × 16 × 8) × 5 SDRAMs ×72 4096MB
8Gb (64M × 16 × 8) × 5 SDRAMs × 2 ranks ×72 8192MB
(1) The ECC device can be either ×8 or ×16 as long as the number of row and column address bits match for all devices in the memory array.