SPRABJ8B September   2022  – November 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2 V
        2. 2.5.1.2 Digital/Analog I/O Power 3.3 V
    6. 2.6 e-Fuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 OSPI/QSPI Memory Implementation
    3. 5.3 ROM OSPI/QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Analog Peripherals
    1. 9.1 General Analog Peripheral Routing Guidelines
      1. 9.1.1 Resolver ADC Routing Guidelines
  13. 10Layer Stackup
    1. 10.1 Key Stackup Features
  14. 11Vias
  15. 12BGA Power Fan-Out and Decoupling Placement
    1. 12.1 Ground Return
    2. 12.2 1.2 V Core Digital Power
      1. 12.2.1 Key Layout Considerations
    3. 12.3 3.3 V Digital and Analog Power
      1. 12.3.1 Key Layout Considerations
    4. 12.4 1.8 V Digital and Analog Power
      1. 12.4.1 Key Layout Considerations
  16. 13References
  17.   Revision History

10.1 Key Stackup Features

  • Standard 62 mil total thickness
  • 4, optionally controlled impedance routing layers on L1, L3, L4 and L6.
  • All signal and power layers all have adjacent ground reference for controlled impedance planning and EMI performance
  • The use of a thicker, 28 mil center core layer, relative to the 4 mil, L2-L3 and L4-L5 dielectric layers, allows for L3 and L4 copper layers to be used as controlled impedance, embedded Microstrip or Stripline routing layers internally due to the low broad-side coupling between L3 and L4.
  • Minimal dielectric thickness between L4 power and L5 GND return layers for best plane capacitance performance, aiding power integrity and EMI.
  • Example fan-out with all through-hole via layer transitions – no micro-via or via-in-pad necessary.
Table 10-1 LP-AM263 Layer Utilization
Layer Number Comment
Copper 1 (Top) Top layer mounting and signal routing
Copper 2 Ground return plane
Copper 3 Embedded Microstrip/Stripline signal routing and power routing
Copper 4 Embedded Microstrip/Stripline and power routing
Copper 5 Ground return plane
Copper 6 (Bottom) Bottom layer mounting and signal routing
Table 10-2 Controlled Impedance Planning Options
Layer Number Reference Layer Number Structure Name (1) Trace Width (mils) Trace Separation (mils) Target Impedance (Ω) Calculated Impedance (Ω) Notes
L1 L2 Coated Microstrip 5.300 0.000 50.000 50.140
L1 L2 Edge Coupled Coated Microstrip 4.200 5.000 90.000 89.830 L1, USB differential
L1 L2 Edge Coupled Coated Microstrip 4.000 7.700 100.000 99.840
L1 L2 Edge Coupled Coated Microstrip 4.100 6.800 120.000 120.030
L3 L3 Offset Stripline 4.750 0.000 50.000 49.960
L3 L2 Edge Coupled Offset Stripline 4.000 6.000 90.000 90.040 L3, USB differential
L3 L2 Edge Coupled Offset Stripline 3.500 8.100 100.000 99.880
L3 L2 Edge Coupled Offset Stripline 4.000 12.000 100.000 100.160
L6 L5 Coated Microstrip 5.300 0.000 50.000 50.140
L6 L5 Edge Coupled Coated Microstrip 4.200 5.000 90.000 89.830
L6 L5 Edge Coupled Coated Microstrip 4.000 7.700 100.000 99.840
L6 L4 Edge Coupled Coated Microstrip 4.100 6.800 120.000 120.030
(1) All impedance calculated using Polar 2D field solver on given copper and dielectric thicknesses, widths and dissipation constants.