SPRABJ8B September   2022  – November 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2 V
        2. 2.5.1.2 Digital/Analog I/O Power 3.3 V
    6. 2.6 e-Fuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 OSPI/QSPI Memory Implementation
    3. 5.3 ROM OSPI/QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Analog Peripherals
    1. 9.1 General Analog Peripheral Routing Guidelines
      1. 9.1.1 Resolver ADC Routing Guidelines
  13. 10Layer Stackup
    1. 10.1 Key Stackup Features
  14. 11Vias
  15. 12BGA Power Fan-Out and Decoupling Placement
    1. 12.1 Ground Return
    2. 12.2 1.2 V Core Digital Power
      1. 12.2.1 Key Layout Considerations
    3. 12.3 3.3 V Digital and Analog Power
      1. 12.3.1 Key Layout Considerations
    4. 12.4 1.8 V Digital and Analog Power
      1. 12.4.1 Key Layout Considerations
  16. 13References
  17.   Revision History

8.1 General Digital Peripheral Routing Guidelines

The following general routing recommendations should be followed throughout an AM263x or AM263Px PCB design. The 45nm LVCMOS process I/O can produce relatively fast edge-rates. Without transmission-line effects planned for, this can result in severe overshoot/undershoot even with relatively short traces on the PCB. These uncontrolled level transitions can damage associated components by presenting attached I/O with over/under-voltage conditions. Additionally, these uncontrolled transitions can radiate excessively which creates cross-talk and EMI compliance problems.

To mitigate these problems:

  • Route all digital I/O as controlled impedance transmission-lines (Microstrip/Stripline)
  • Place series termination near each AM263x or AM263Px transmit pin and attached transmit pins of associated IC
    • The values and performance of these termination resistors should be validated during wake-up of new PCB hardware.
    • In some cases, these termination resistors may not be required, but they should only be removed or eliminated from the design after testing
  • Route with solid ground return planes on adjacent layers
  • Route with ground return rings surrounding constantly switching signals (clocks, EPWM)
  • Route with ground return rings surrounding sensitive analog signals (ADC/DAC channels, VREF)

For additional guidance on peripheral routing please reference High-speed Interface Layout Guidelines.