3 Compensate the Component Variations During the SR Clamp Mode

As shown in Figure 1-1, normally most of present products will define a fixed value for the SR clamping width based on the ideal resonant tank parameters during the SR clamp mode. However, since the values of resonant capacitors and inductors must be different from part to part and might change over the lifetime. It is common to select a minimum resonant period for the SR clamp mode based on the possible variation ranges of resonant tank parameters, in order to avoid unexpected negative current. That means most of the products in mass production could not operate with the best efficiency, due to SR MOSFET turns off too early. It is also challenging for the time and cost required if the calibration process of the resonant tank is implemented during the manufacture process.

In order to compensate the component variations for the resonant tank and achieve optimal SR turn-off edge control, CLB module inside C2000 devices is used together with the DTC feedback from UCD7138.

As shown in Figure 3-1, the DTC signal from UCD7138 is fed into C2000, as one of the input signals for CLB module. The basic idea to is use CLB to count the body diode conduction time with the DTC signal under the SR clamp mode, so as to increase the SR on-time with turn off edge, until the captured duration time for the DTC low event is within the targeted value, shown in Figure 3-1.

The detailed steps are as follows.

1. During the initialization, the SR clamp on-time is set with the minimum value of resonant period/2, with the possible maximum values of the resonant capacitors and inductors.
2. Leverage CLB counter to detect the body diode conduction time. Since the UCD7138 turn-off edge is determined by the IN signal only, the detection window for the effective DTC low event is between the falling edge of the SR PWM signal and the rising edge of DTC signal. Thus, a counter of CLB could be used here.

   Since the counter will always reset to 0 if the “RESET” input remains high, the IN signal can be used to trigger the counter to start counting after the falling edge. Then, the inverting DTC signal is set as the MODE_0 input(active high to enable the counting). With MODE_1 set to 1, in this way, the duration of the DTC low event could be obtained.

3. During the SR clamp mode, increase the SR clamp on-time step by-step until the obtained DTC low time reduces to be less than a targeted value. Since such adjustment is not time critical, the software task could be placed in a background loop or a normal interrupt, with less CPU bandwidth occupied. In addition, the adjustment could be set as one-time effort or periodical event during the runtime depending on actual system requirements.

The below code snippets give an example for the SR clamp on-time adjustment, where the CLB counter value is required to be obtained through the R0 register in the High Level Controller (HLC) of CLB, and SR_clamp_mode refers to the SR clamp operation mode, and clamp_ajust_flag is used to indicate the adjustment is done, if the body diode conduction time after SR turns off is within 50 ns, for example.

if(clamp_ajust_flag && SR_clamp_mode)
{
   counter1_low = CLB_getRegister(CLB1_BASE, CLB_REG_HLC_R0);
   if(counter1_low>5)
   {
   SR_clamp_time=SR_clamp_time+2;
 }
 else
 {
   clamp_ajust_flag=0;
 }
}