SPRAC94D September   2018  – March 2022 AFE030 , AFE031 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1 FSK Overview
  3. 2 Hardware Overview
    1. 2.1 Block Diagram
    2. 2.2 Hardware Setup
  4. 3 Interfacing With the AFE03x
    1. 3.1 Configuring the AFE031
  5. 4 Transmit Path
    1. 4.1 FSK Example Specifications
    2. 4.2 PWM Mode
      1. 4.2.1 Software Implementation
      2. 4.2.2 Testing Results
      3. 4.2.3 HRPWM vs. EPWM
    3. 4.3 DAC Mode
      1. 4.3.1 Software Implementation
      2. 4.3.2 Testing Results
      3. 4.3.3 OFDM Ability
    4. 4.4 Porting TX to LAUNCHXL-F280049C
      1. 4.4.1 PWM Mode Specific Porting
      2. 4.4.2 DAC Mode Specific Porting
  6. 5 Receive Path
    1. 5.1 Receive Path Overview
    2. 5.2 Receiver Software Implementation
      1. 5.2.1 Initial Setup and Parameters
      2. 5.2.2 Interrupt Service Routines
      3. 5.2.3 Run Time Operation
      4. 5.2.4 Testing Results
      5. 5.2.5 System Utilization
      6. 5.2.6 Device Dependency and Porting
    3. 5.3 Tuning and Calibration
      1. 5.3.1 Setting the AFE03X's PGAs
      2. 5.3.2 Automatic Gain Control (AGC)
      3. 5.3.3 Setting the Bit Detection Threshold
      4. 5.3.4 FSK Correlation Detector Library
    4. 5.4 Porting RX to LAUNCHXL-F280049C
  7. 6 Interfacing With a Power Line
    1. 6.1 Line Coupling
    2. 6.2 Coupling to an AC Line
      1. 6.2.1 Low Voltage Capacitor
      2. 6.2.2 The Ratio of the Transformer
      3. 6.2.3 HV Capacitor
      4. 6.2.4 HV Side Inductor
    3. 6.3 Coupling to DC Line
    4. 6.4 Protection Circuit
      1. 6.4.1 Metal Oxide Varistors
      2. 6.4.2 Transient Voltage Suppressors
      3. 6.4.3 Current Steering Diodes
    5. 6.5 Determining PA Power Supply Requirements
  8. 7 Summary
  9. 8 References
  10. 9 Schematics
    1. 9.1 Schematics (PWM Mode)
    2. 9.2 Schematics (DAC Mode)
  11. 10Revision History

4.2 PWM Mode

In PWM mode, the C2000 F28379D generates two symmetric PWM signals that go directly into the AFE device. The two symmetric PWM signals are 66% and 33% duty cycle. These signals are added together inside the AFE device and create a waveform that has the least amount of noise. Figure 4-1 shows how this addition works.

GUID-72C3A0C7-937A-4980-858F-A4F03975A289-low.jpgFigure 4-1 PWM Addition

The path of the PWM signals is shown in Figure 4-2. The PWM signals go into the low-pass filter internal to the AFE030/1 device, and are added together to create the above PWM1+PWM2 waveform.

GUID-A240D75B-094C-45DF-9227-7C29F42E83E9-low.gifFigure 4-2 PWM Transmit Path

The gains witnessed at certain frequencies at the output of the internal TX low-pass filter are shown in Figure 4-3.

GUID-E9B99E90-03AA-4462-8E92-D50C72F0799F-low.pngFigure 4-3 TX Filter Gain vs. Frequency

Next, the signal goes through a low-pass filter, PGA, another low-pass filter, and finally out of the PA. The external low-pass filters can be tuned to filter the desired frequencies shown in Table 4-2.

Table 4-2 External R and C Values to Increase Filter Response in PWM Applications
Frequency BandR (Ω)C (nF)
SFSK: 63 kHz, 74 kHz5102.7
CENELEC A5101.5
CENELEC B,C,D5101