SPRACA7A October   2017  – September 2022 TMS320F28075 , TMS320F28075-Q1 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   C2000™ Hardware Built-In Self-Test
  2.   Trademarks
  3. 1Introduction
    1. 1.1 HWBIST Overview
      1. 1.1.1 HWBIST Working In-System
    2. 1.2 HWBIST Failure Response
    3. 1.3 Advantages of Using HWBIST In-System
  4. 2Using HWBIST In-System
    1. 2.1 Fundamental HWBIST Operation
      1. 2.1.1 Initializing the HWBIST Controller
      2. 2.1.2 Executing HWBIST
        1. 2.1.2.1 Executing HWBIST Micro-Run
        2. 2.1.2.2 Executing HWBIST Full-Run
      3. 2.1.3 Error Management
    2. 2.2 Managing HWBIST on Dual-Core Device
      1. 2.2.1 Semaphore Management
      2. 2.2.2 Interprocessor Communications
    3. 2.3 System Considerations When Using HWBIST
      1. 2.3.1 Interrupt Latency
      2. 2.3.2 Power Considerations
      3. 2.3.3 HWBIST Memory Requirements
      4. 2.3.4 Injecting Errors
    4. 2.4 Debugging HWBIST In-System
  5. 3References
  6. 4Revision History

2.2 Managing HWBIST on Dual-Core Device

F2837xD and F2838xD dual-core devices support HWBIST testing on each core. Only one core at a time can run HWBIST. To manage this HWBIST controller, certain semaphore registers allow one processor to own the HWBIST controller until it is complete. Upon completion of a full HWBIST, the tested processor should release the semaphore control to the other processor so that it can run the HWBIST.