As stated earlier, some C2000 devices support the use of the HWBIST to screen the CPU for logic failures in the system rather than just during device manufacture testing. Figure 1-2 shows a block diagram, which includes the additional circuitry to support this option.

When using HWBIST in a device test environment, testers manage each targeted logic portion to provide the overall test of the device. However, when the device is in a system, aspects of the system may be adversely affected by the activity of the under test targeted logic. These aspects are both on the device and outside the device. For this reason, the HWBIST includes a barrier around the targeted logic so that the activity of the HWBIST testing is isolated from the rest of the system. The CPU is disconnected from peripherals and interrupt signals during a micro-run test. After the test, the core is reconnected to these signals. This is known as core bounding. In Figure 1-2, the isolation barrier is shown in green. It is also true that the logic under test must be isolated from activity elsewhere in the system. This barrier provides this as well.

However, if the system must get the attention of the CPUs under test, then it can provide interrupts. These interrupts are captured in a buffer and provided to the CPU logic under test when the BIST controller releases the targeted logic. The complete coverage testing of the targeted logic takes a while. The higher the coverage goal, the longer it takes. The BIST controller in the C2000 devices executes and validates the total coverage seeds in small portions to minimize the latency to these captured interrupts. This also addresses some of the power concerns of the higher transistor switching rates generated through the parallel scan paths.

In extreme situations, the system resources can generate an NMI that halts the HWBIST operation and brings back the CPU under test using a HWBIST Reset. As soon as the context restore is complete, the NMI vector is taken and the NMI service routine can decode the NMI flag register to determine the source of the interruption. The NMI will trap before the HWBIST software returns to the calling sequence. The user application must manage the NMI responses accordingly.

A significant difference between device-manufacturing HWBIST and in-system HWBIST, is that the device tester communicates with the BIST controller over a test port, while the in-system HWBIST uses the CPU to communicate with the BIST controller. The CPU that the HWBIST is testing, is the CPU which manages the HWBIST controller. More specifically, the C28x CPU under test, where all the latches are changed multiple times, controls the BIST operation.

Here is how this process works. Code running on the CPU does the following:

1. Initializes the mode of operation in the HWBIST, mapping the CPU reset to respond to the HWBIST return to service routine specially coded for return from HWBIST.
2. Turns on the Interrupt Capture Buffer.
3. Saves the context of the CPU and the associated code-based accelerators.
4. Starts up the small time-slice of the HWBIST execution. At this point the CPU stops being a CPU and starts being logic under test.
5. Upon completion of the small time-slice of the HWBIST execution the HWBIST controller:
   • Captures the results in a status register. If a logic failure is detected, the BIST controller generates a NMI to the CPU.
   • Generates CPU reset to the CPU logic:
     • This reset puts the CPU into a known and controlled state.
     • Upon release of this reset, the logic under test becomes a CPU again.
6. The CPU executes the HWBIST reset service routine:
   • Restores saved context
   • Shuts down residuals of the HWBIST controller operation
   • Releases the interrupts stored in the Interrupt Capture Buffer
   • Returns to the calling sequence where the HWBIST status register can be read

While the HWBIST is executing, other aspects of the system can operate as well. As previously mentioned, interrupts coming from off-chip or on-chip sources are saved in the Interrupt Capture Buffer. However, triggers mapped to DMA channels are processed while the HWBIST is actively testing the CPU. For example, system-related commands from a SCI or I2C port can be collected and moved from the port to system memory to be processed as soon as Step 6 is completed. This is because all the device buses are isolated using the HWBIST Barrier.

All of the operations listed in the previous outline are executed in the C2000 Software Diagnostic Library (SDL), which is a component of C2000Ware. The SDL provides implementations of functional safety software mechanisms to help system developers meet their safety goals. The details of how the application code can call the provided HWBIST driver are documented in the User's Guide that is included in the SDL package. The SDL User's Guide is the best source for device-specific details about HWBIST, such as supported diagnostic coverage and execution time. Look for this document in <C2000Ware install directory>/libraries/diagnostic/<device>/docs.