SPRACA7A October   2017  – September 2022 TMS320F28075 , TMS320F28075-Q1 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   C2000™ Hardware Built-In Self-Test
  2.   Trademarks
  3. 1Introduction
    1. 1.1 HWBIST Overview
      1. 1.1.1 HWBIST Working In-System
    2. 1.2 HWBIST Failure Response
    3. 1.3 Advantages of Using HWBIST In-System
  4. 2Using HWBIST In-System
    1. 2.1 Fundamental HWBIST Operation
      1. 2.1.1 Initializing the HWBIST Controller
      2. 2.1.2 Executing HWBIST
        1. 2.1.2.1 Executing HWBIST Micro-Run
        2. 2.1.2.2 Executing HWBIST Full-Run
      3. 2.1.3 Error Management
    2. 2.2 Managing HWBIST on Dual-Core Device
      1. 2.2.1 Semaphore Management
      2. 2.2.2 Interprocessor Communications
    3. 2.3 System Considerations When Using HWBIST
      1. 2.3.1 Interrupt Latency
      2. 2.3.2 Power Considerations
      3. 2.3.3 HWBIST Memory Requirements
      4. 2.3.4 Injecting Errors
    4. 2.4 Debugging HWBIST In-System
  5. 3References
  6. 4Revision History

2.1.3 Error Management

A failing condition from a HWBIST execution is a serious situation. If this occurs, then the behavior of the CPU that failed cannot be ensured. Code that takes appropriate action to gracefully shut down the system must be included. This can be done by decoding the return value of STL_HWBIST_runFull() or STL_HWBIST_runMicro().

The code can be managed through a trap to the NMI. This is the quicker method for managing a HWBIST failure, especially in the case of a dual CPU device, because the NMI is sent to both CPUs. To take advantage of the NMI traps, the system code must do the following:

  1. Clear any NMI trap residual from the NMI flag register: 
    SysCtl_clearNMIStatus(STL_HWBIST_NMI_CPU1_HWBISTERR);
    SysCtl_clearNMIStatus(STL_HWBIST_NMI_CPU2_HWBISTERR);
  2. Map the NMI vector to the Interrupt Service Routine that handles HWBIST: 
    Interrupt_register(INT_NMI, STL_HWBIST_errorNMIISR);
  3. Enable the PIE controller: 
    Interrupt_enablePIE();

    The ENPIE bit of the PIECTRL register is set on the CPU being tested by the HWBIST software, but it must also be set on the other CPU (in a dual-CPU device) for it to respond to the failure.

For more details about the NMIFLG register and the HWBIST flags it contains, see the device-specific Technical Reference Manual.