SPRACC0A November   2017  – November 2020 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1

 

  1.   Trademarks
  2. 1 Introduction and Scope
  3. 2 SRAM Bit Array
  4. 3 Sources of SRAM Failures
    1. 3.1 Manufacturing Defects
      1. 3.1.1 Time Zero Fails
      2. 3.1.2 Latent Fails
    2. 3.2 Circuit Drift With Usage
    3. 3.3 Circuit Overstress
    4. 3.4 Soft Errors
      1. 3.4.1 Radioactive Events
      2. 3.4.2 Dynamic Voltage Events
      3. 3.4.3 Summary of Error Sources
  5. 4 Methods for Managing Memory Failures in Electronic Systems
    1. 4.1 Start-Up Testing
    2. 4.2 In-System Testing
    3. 4.3 Parity Detection
    4. 4.4 Error Detection and Correction (EDAC)
    5. 4.5 Redundancy
  6. 5 Comparisons and Conclusions
  7. 6  C2000 Memory Types Example
    1. 6.1 TMS320F2837xD
  8. 7 Memory Types
    1. 7.1 Dedicated RAM (Mx and Dx RAM)
    2. 7.2 Local Shared RAM (LSx RAM)
    3. 7.3 Global Shared RAM (GSx RAM)
    4. 7.4 CPU Message RAM (CPU MSGRAM)
    5. 7.5 CLA Message RAM (CLA MSGRAM)
  9. 8 Summary
  10. 9 References
  11. 10Revision History

2 SRAM Bit Array

Information is stored into SRAM as words. The word length varies per the needs of the storage. 32-bit words are used for this discussion. The bits of the word are stored in an array of bits. However, the physical position of each individual bit is optimized to the specifics of the semiconductor process. The array is a matrix with rows and columns. In the example below, there are N rows of 8 words each. If N = 256 that comes to 256x8x32 = 65,536 bits or 2048 words of SRAM.

Note how the bits of an individual word are not physically adjacent to each other, but rather all the bits of 1 D-input/Q-output are adjacent. The bits of an individual word are physically separated by 7 bits from other words. This improves both the size of the physical array and the routing of the D/Q signals. You will see later how this improves the error detect-ability of multi-bit failure mechanisms.

The following shows values in three words as follows:

Word(0) = 1 … 0 1b    Row0, Column0
Word(1) = 1 … 1 0b    Row0, Column1
Word(7) = 1 … 0 0b    Row3, Column7
Table 2-1 SRAM Bit Array
D0 D1 D31
Row Col
0 1 2 … 7 0 1 2 … 7 0 1 2 … 7 Column
N-1
…
5
4
3 0 0 1
2
1
0 1 0 0 1 1 1

The physical organization of bit cells in an array may vary for many reasons, but this figure provides a good example to discuss. This example shows a column multiplexor factor of 8, meaning there are 8 bits on a row for each Q/D. On a memory read the row is selected and then the column address provides the decode information for which specific bit will go out the Q. On a memory write, the column decodes define specifically which bits well be written to on the selected row. The sub-array (256x8) for each D/Q is called a stick.

Larger memory arrays are often organized with even higher column mux factors.