SPRACI9A October   2018  – July 2021 AM6526 , AM6528 , AM6546 , AM6548

 

  1.   Trademarks
  2. 1Introduction
  3. 2Recommendations Specific to the AM65x/DRA80x
    1. 2.1  EVM versus Data Sheet
    2. 2.2  Power
    3. 2.3  Reset
    4. 2.4  Boot Modes
    5. 2.5  Unused Signals
    6. 2.6  Clocking
    7. 2.7  System Issues
    8. 2.8  Low Power Considerations
    9. 2.9  DDR
    10. 2.10 MMC
    11. 2.11 OSPI and QSPI
    12. 2.12 GPMC NAND
    13. 2.13 I2C
    14. 2.14 CPSW Ethernet
    15. 2.15 ICSSG
    16. 2.16 USB
    17. 2.17 SERDES - USB3
    18. 2.18 SERDES - PCIe
    19. 2.19 JTAG and EMU
  4. 3References
  5. 4Revision History

SERDES - PCIe

  • Have you planned for the routing in the PCIE interface? For detailed recommendations on proper PCIE SERDES signal connection and routing, see the High-Speed Interface Layout Guidelines Application Report. Add appropriate constraints or routing requirements to your schematic. This will vary from tool to tool.
  • Have you connected the correct SERDES pairs for PCIE operation? The AM65x includes two SERDES sets of transmit and receive pairs named SERDES0 and SERDES1. Each can support a number of SERDES interfaces, but the correct SERDES pairs must be used for the correct interface. SERDES0 and SERDES1 can each support two separate PCIE 1-lane connections, but if a PCIE 2-lane connection is needed, the pairs must be connected in the correct order. SERDES0 signals should be connected to the PERp0/n0 and PETp1/n1 pairs, and the SERDES1 signals should be connected to the PERp1/n1 and PETp1/n1 signals for a two-lane PCIE connection.
  • Have you included DC-blocking capacitors in the correct location? DC-blocking capacitors are required for PCIE transmit and receive pairs, but the capacitors should be placed closer to the PCIE transmitter. If a PCIE connector is used in the design, the receive pair will be connected directly to the connector. The DC-blocking caps for the receive pair are present on the device connected to the PCIE connector.