Have you used the output of the power model and estimates
from the rest of your design to determine the power solution needed? The
power needed for each rail of the AM65x/DRA80x SoC varies based on the
interfaces used and the environment in which it is operating. Power requirements
must be determined using the power model.
Have you checked that the correct voltages are applied to
the correct power pins on the device? The AM65x/DRA80x SoC includes a
number of power rails that must be powered with the correct voltage for proper
operation.
Have you checked that all signals connected to each of
these domains are operating at the expected voltage level? The
AM65x/DRA80x SoC includes twelve dual-voltage I/O domains configured for either
3.3 V or 1.8 V. All signals connected to these domains must match the voltage
level provided to the associated VDDSHVx supply rail. The AM65x/DRA80x I/O
buffers are not failsafe. The voltage for the VDDSHVx rail must be present
before any voltage is applied to the associated I/Os.
Have you checked that the VDDS[2:0]_WKUP and VDDS[8:0] for
all rails configured for 1.8 V are connected to the 1.8-V I/O power
supply?Have you checked that the VDDS[2:0]_WKUP and VDDS[8:0] for all rails
configured for 3.3 V are connected to the proper internal LDO? To
sequence correctly, VDDS[2:0]_WKUP and VDDS[8:0] must be supplied by either the
1.8-V I/O power supply or an internal I/O bias LDO, depending on the voltage of
the rail.
Do you have the proper capacitor value connected to each
output of the internal LDOs? The AM65x/DRA80x SoC includes seventeen
internal LDOs with the output of each connected to a pin on the device. The LDOs
require an output capacitor connected to each of these pins.
Does your design meet the power sequencing requirement in
the data manual? Proper power supply sequencing in proper correlation
with resets and clocks is required. For the recommended power sequencing
requirements, see the device-specific data sheet.
Are the filters specified in the Technical Reference manual
included for the VDDA_x supply pins? AM65x/DRA80x devices contain
multiple analog power pins that provide power to sensitive analog circuitry such
as PLLs, DLLs, and SERDES buffers and terminations. These must be attached to
filtered power sources.
Does your design include the correct termination for your
selected DDR interface type? The DDR3 and DDR4 interfaces both require a
VTT termination at the end of the flyby chain for the DDR address, command and
control. The VTT termination voltage is generated using a special push/pull
termination regulator specifically designed to meet the VTT requirements.
Are the DDR_VREF0 and DDR_VREF_ZQ pins left unconnected
with no external voltage applied? The AM65x/DRA80x generates the DDR
reference voltage internally. The DDR_VREF0 and DDR_VREF_ZQ pins are intended
for observation only.
Has the PDN analysis been performed and are the proper
values and number of bypass capacitors included in your design? Use low
ESL capacitors and mount them with short traces to keep the mounting inductance
very low. This is required to meet the specified PDN impedance. For more
details, see Sitara Processor Power Distribution Networks:
Implementation and Analysis.
Does your design include properly implemented current
measurement capabilities? Zero ohm resistors in line with core and other
power sections of the board are recommended for initial PCB prototype builds if
you want to measure power. You should then remove the resistor in production
builds and connect the power planes with wide copper or multiple vias. Power
measurement is the purpose of these resistors in the EVM designs. The
implementation of these resistors adds inductance and resistance that can impair
power supply and power distribution performance. Current measurement on a single
part should never be substituted for the values provided by the Power Model
spreadsheet.