SPRACJ6A October   2018  – December 2022 AM6526 , AM6528 , AM6546 , AM6548

 

  1.   Trademarks
  2. 1 Introduction
    1. 1.1 Before Getting Started
    2. 1.2 Device (Processor) Selection
    3. 1.3 Technical Documentation
    4. 1.4 Design Documentation
  3. 2 System Block Diagram
    1. 2.1 Creating the System Block Diagram
    2. 2.2 Selecting the Boot Mode
    3. 2.3 Confirming Pin Multiplexing Compatibility
  4. 3 Power Supply
    1. 3.1 Power (Supply) Rails
      1. 3.1.1 Internal LDOs for IO groups
      2. 3.1.2 Dual-Voltage LVCMOS I/Os
      3. 3.1.3 Dual-Voltage Switching SDIO I/Os
    2. 3.2 Determining System Power Requirements
    3. 3.3 Power Supply Filters
    4. 3.4 Power Supply Decoupling and Bulk Capacitors
    5. 3.5 Power Supply Sequencing
  5. 4 Clocking
    1. 4.1 System Clock Inputs
    2. 4.2 Single-Ended Clock Sources
    3. 4.3 Unused Clock Inputs
  6. 5 JTAG
    1. 5.1 JTAG / Emulation
      1. 5.1.1 Configuration of JTAG / Emulation
      2. 5.1.2 System Implementation of JTAG / Emulation
      3. 5.1.3 JTAG Termination
  7. 6 Device Configurations and Initialization
    1. 6.1 Device Reset
    2. 6.2 Boot Modes
    3. 6.3 Watchdog Timer
  8. 7 Peripherals
    1. 7.1 Selecting Peripherals Across Functional Domains
    2. 7.2 Ethernet Interface
    3. 7.3 Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU-ICSSG)
    4. 7.4 Universal Serial Bus (USB) Subsystem
  9. 8 I/O Buffers and Termination
  10. 9 Power Consumption and Thermal Solutions
    1. 9.1 Power Consumption
    2. 9.2 Power Savings Modes
    3. 9.3 Guidance on Thermal Solution
  11. 10Schematic Recommendations
    1. 10.1 Selection of Component and Values
    2. 10.2 Schematics Development
    3. 10.3 Reviewing the Schematics
    4. 10.4 Floor planning of the PCB
  12. 11Layout and Routing Guidelines
    1. 11.1 Escape Routing Guidelines
    2. 11.2 DDR Board Design and Layout Guidelines
    3. 11.3 High-Speed Differential Signal Routing Guidance
  13. 12Terminology
  14. 13References
  15. 14Revision History

6.1 Device Reset

The processor can be reset in several ways. The methods are described in detail in the device-specific data sheet and TRM.

The device includes four external reset pins (MCU_PORz, MCU_RESETz, PORz, and RESETz) and four reset status pins (MCU_PORz_OUT, MCU_RESETSTATz, PORz_OUT, and RESETSTATz). Be sure to provide the terminations recommended in the data sheet.

Additional reset modes are available through internal registers and emulation.

The device integrates an on-chip Power-on-Reset (POR) generator. Additionally, this device supports an external POR generation through a PORz and MCU_PORz input pin. The MCU_BYPASS_POR pin selects the POR source. When the MCU_BYPASS_POR pin is set high at power-up, on-chip POR generation will be completely bypassed and the external POR used. When it is low, the POR is generated internally. However, the four external reset inputs must all be pulled high to enable this internal POR generation.

Note that TI recommends implementing RESET logic using AND gate for on-board Media and Data Storage devices and other peripherals as applicable. One of the AND gate input shall be controlled by processor GPIO pin with provision to isolate. Other AND gate input shall be the Main Domain POR status output (PORz_OUT) Signal. Ensure the reset outputs are terminated as per the device recommendations.

The 3.3 V power source for the SD Card needs to be routed through an external power switch that can be controlled. This controlled power switch is required to reset the SD Card since cycling power to the card is the only way to reset the card back to its default state.

For more information, see the TMDX654GPEVM (AM65x evaluation module (EVM)) and TMDX654IDKEVM (AM65x industrial development kit (IDK)) schematics.