SPRACN3 September   2019 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04

 

  1.   Using ARM ROM Bootloader on Keystone II Devices
    1.     Trademarks
    2. 1  Keystone2 Boot loader Overview
    3. 2  Boot Examples Package Download
    4. 3  Software Dependencies
    5. 4  Supported Hardware
    6. 5  Software Features
    7. 6  Directory Structure
    8. 7  Building the Examples
    9. 8  Description of the Examples
      1. 8.1 Single Stage Boot Examples
      2. 8.2 Multi-Stage Boot Example
      3. 8.3 Boot Media-Specific Details
        1. 8.3.1 SPI Boot Example
        2. 8.3.2 I2C Boot Examples
        3. 8.3.3 NAND Examples
        4. 8.3.4 UART Boot Examples
        5. 8.3.5 Ethernet boot examples
        6. 8.3.6 K2E Ethernet Boot Errata Workaround
      4. 8.4 Flashing and Running Boot Examples
        1. 8.4.1 Dip Switch Settings
        2. 8.4.2 Running I2C EEPROM example
        3. 8.4.3 Running SPI NOR Example
        4. 8.4.4 Running NAND Example
        5. 8.4.5 Running UART Example
        6. 8.4.6 Running Ethernet Examples
    10. 9  Boot Utilities
    11. 10 Frequently Asked Questions (FAQ)
    12. 11 References

8.3.4 UART Boot Examples

UART boot is a blob boot in which the Boot ROM configures the PLL based on the reference clock setting provided from the boot switches. The boot ROM configures the UART to the baud rate of 115200 bps and sends a ping character to indicate the device is ready to accept the image. The device loads the blob boot image at the base of the MSMC. On K2E devices, you have the option to change the load address for the boot images but on K2H the second stage will also need to be loaded at the base of MSMC. It was also observed that the you need to enable MMU table on the Arm on blob boot modes.

NOTE

On K2H devices, the boot ROM does not invalidate the Instruction cache so the example on K2H loads the two stages in non-overlapping memory. However, the first instruction that redirects the device to the entry point of the application needs to execute from the base of MSMC, so the instruction cache in the first stage needs to also be invalidated. To create non-overlapping 2 stages, use a 1K random memory segment in the first stage.