2.1 Functional Overview
Figure 2 shows a functional view of the time sync network in the AM65xx device, where sync signals from each protocol interfaces are interconnected via the Time Sync network.
With this network, the following cross-protocol synchronization can be achieved:
- Time master - device can send synchronized master clock to downstream using any of these interfaces:
- PCIe PTM Responder (Ports configured as RC)
- Industrial Ethernet ports (IEEE 1588 or 802.1AS)
- Ethernet port(IEEE 1588 or 802.1AS)
- Explicit sync via hardware pins
- Time slave - receives global system time from the following interfaces
- PCIe PTM Responder (Ports configured as RC)
- Industrial Ethernet ports (IEEE 1588 or 802.1AS)
- Ethernet port(IEEE 1588 or 802.1AS)
- Explicit sync via hardware pins
- Relays global system time by receiving master time from one interface/protocol and syncing to another interface so the interface can update downstream devices
- Adjustment of on-chip Timers and Timer Managers whose timer tick can be tuned to the received global time base
- Supports hardware-based detection of clock differences between local clock and global clock, allowing CPU internal timers to use adjusted time-bases