SPRACP7 October   2019 AM6526 , AM6528 , AM6546 , AM6548

 

  1.   AM65xx Time Synchronization Architecture
    1.     Trademarks
    2. 1 Introduction
    3. 2 AM65xx Time Sync Architecture
      1. 2.1 Functional Overview
      2. 2.2 Time Sync Components
        1. 2.2.1 TSR and CER
        2. 2.2.2 NAV_CPTS
        3. 2.2.3 DM_Timers and Timer Managers
        4. 2.2.4 PCIe With PTM
        5. 2.2.5 IEP Timers in ICSSGx
        6. 2.2.6 CPSW
        7. 2.2.7 GTC
    4. 3 Time-Synchronization Examples
      1. 3.1 AM65xx as the Time Master Server
      2. 3.2 Multi-Domain Time Synchronization Across PCIe Interconnect
      3. 3.3 Hand-Over and Recovery
    5. 4 Summary
    6. 5 References

2.2.7 GTC

The Global Time-base Counter is a free running counter in the SoC, that provides Gray-coded times tamps to the A53 CPUs, where internal generic timers are derived. The GTC is a monotonic counter. There are multiple clock sources to choose for GTC's clock tick, but non of the clock source are adjustable. Therefore, A53 CPU generic timers are not tunable by hardware; instead, software adjustment should be considered if the system is required to adjust its timer based on a received master clock. Figure 7 shows how GTC is integrated with the Cortex A53 CPU cluster.

spracp7-fig7-gtc.gifFigure 7. GTC and Clock Selection