SPRACP7 October   2019 AM6526 , AM6528 , AM6546 , AM6548

 

  1.   AM65xx Time Synchronization Architecture
    1.     Trademarks
    2. 1 Introduction
    3. 2 AM65xx Time Sync Architecture
      1. 2.1 Functional Overview
      2. 2.2 Time Sync Components
        1. 2.2.1 TSR and CER
        2. 2.2.2 NAV_CPTS
        3. 2.2.3 DM_Timers and Timer Managers
        4. 2.2.4 PCIe With PTM
        5. 2.2.5 IEP Timers in ICSSGx
        6. 2.2.6 CPSW
        7. 2.2.7 GTC
    4. 3 Time-Synchronization Examples
      1. 3.1 AM65xx as the Time Master Server
      2. 3.2 Multi-Domain Time Synchronization Across PCIe Interconnect
      3. 3.3 Hand-Over and Recovery
    5. 4 Summary
    6. 5 References

2.2.4 PCIe With PTM

The PCIe controllers are shown in Figure 5 support Precision Time Measurement (PTM) protocol. Figure 3 shows how the PTM module is integrated with the embedded CPTS in the PCIe controller.

In RC mode, the PTM source its master time-base from the 250 MHz pcie_txi clock, which is the pipe clock of the PCIe PHY. In EP mode, a reference clock (pcie_ptmrclk) can be selected from a set of mux input, and the reference clock is used to drive a counter in the PTM core, which subsequently drive out an adjusted output timestamps, based on PTM protocol. To directly use the timestamps as sync events for other subsystems, a selected bit of the 64-bit timestamp bus if output to the TSR. The same event is also sent to the local CPTS as a HWPUSH event so the PCIe-CPTS can directly drive sync events with additional adjustments.

spracp7-fig5-pcie-ptm.gifFigure 5. PCIe PTM Functional View