SPRACP7 October   2019 AM6526 , AM6528 , AM6546 , AM6548

 

  1.   AM65xx Time Synchronization Architecture
    1.     Trademarks
    2. 1 Introduction
    3. 2 AM65xx Time Sync Architecture
      1. 2.1 Functional Overview
      2. 2.2 Time Sync Components
        1. 2.2.1 TSR and CER
        2. 2.2.2 NAV_CPTS
        3. 2.2.3 DM_Timers and Timer Managers
        4. 2.2.4 PCIe With PTM
        5. 2.2.5 IEP Timers in ICSSGx
        6. 2.2.6 CPSW
        7. 2.2.7 GTC
    4. 3 Time-Synchronization Examples
      1. 3.1 AM65xx as the Time Master Server
      2. 3.2 Multi-Domain Time Synchronization Across PCIe Interconnect
      3. 3.3 Hand-Over and Recovery
    5. 4 Summary
    6. 5 References

4 Summary

While protocols are well defined for communication and network protocols, it is equally important to have hardware support within the SoC, to achieve designed time sync precision. It is critical to have the required time-stamping hardware as well as time sync interconnect in the device.

With the deployment of Time Sensitive Networks (TSN) in factory automation, industrial controls, automotive, and rest of Industry 4.0 networks, it became essential for a processor to support multiple time-sync protocols simultaneously, maintaining multiple time domains in the device, as well as cross-protocol synchronization.

The capabilities of the time sync architecture expands far beyond the two example use cases explained in this document. Actual system implementations may implement more flexible synchronization, hand-off mechanisms and robust recovery functions when time masters become non-available.