SPRACQ1 May   2020 TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377S , TMS320F28379D , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

 

  1.   Migration Between TMS320F2837x and TMS320F2838x
    1.     Trademarks
    2. 1 Feature Differences Between F2837x and F2838x
      1. 1.1 F2837x and F2838x Feature Comparison
    3. 2 PCB Hardware Changes
      1. 2.1 VDD Pin
      2. 2.2 VREGENZ Pin
      3. 2.3 Analog Pin Assignment
      4. 2.4 GPIO Pin Assignment
      5. 2.5 controlCARD
    4. 3 Feature Differences for System Consideration
      1. 3.1 New Features in F2838x Device
        1. 3.1.1  Fast Integer Division (FINTDIV)
        2. 3.1.2  VCRC Unit
        3. 3.1.3  EtherCAT Slave Controller (ESC)
        4. 3.1.4  Background CRC (BGCRC)
        5. 3.1.5  Diagnostic Features (PBIST/HWBIST)
        6. 3.1.6  Power Management Bus Module (PMBus)
        7. 3.1.7  Fast Serial Interface (FSI)
        8. 3.1.8  Embedded Real-time Analysis and Diagnostic (ERAD)
        9. 3.1.9  Dual-Clock Comparator (DCC)
        10. 3.1.10 Connectivity Manager (CM)
      2. 3.2 Features Differences/Enhancements in F2838x
        1. 3.2.1 System
          1. 3.2.1.1 Reset
          2. 3.2.1.2 Clocking
            1. 3.2.1.2.1 PLL
            2. 3.2.1.2.2 X1CNT
            3. 3.2.1.2.3 XCLKOUT
          3. 3.2.1.3 Pie Channel Mapping and Interrupt
            1. 3.2.1.3.1 SYS_ERR Interrupt
          4. 3.2.1.4 ERRORSTS Pin
        2. 3.2.2 Watchdog and NMI Watchdog
        3. 3.2.3 Memory
          1. 3.2.3.1 Internal SRAM/ROM
          2. 3.2.3.2 Flash
        4. 3.2.4 Dual Code Security Module (DCSM)
        5. 3.2.5 ROM Code and Peripheral Booting
        6. 3.2.6 External Memory Interface (EMIF)
        7. 3.2.7 Communication Modules
        8. 3.2.8 Control Modules
          1. 3.2.8.1 Enhanced Pulse Width Modulator (ePWM) and ePWM Sync Scheme
          2. 3.2.8.2 Enhanced Capture (eCAP)
          3. 3.2.8.3 Enhanced Quadrature Encoder Pulse (eQEP)
          4. 3.2.8.4 Sigma Delta Filter Module (SDFM)
        9. 3.2.9 Analog Modules
      3. 3.3 Other Device Changes
        1. 3.3.1 Bus Architecture
          1. 3.3.1.1 CLA and DMA Access
        2. 3.3.2 Control Law Accelerator (CLA)
        3. 3.3.3 Direct Memory Access (DMA)
      4. 3.4 Power Management
        1. 3.4.1 LDO/VREG
        2. 3.4.2 POR/BOR
      5. 3.5 Power Consumption
      6. 3.6 GPIO
        1. 3.6.1 GPIO Multiplexing Diagram
    5. 4 Application Code Migration From F2837x to F2838x
      1. 4.1 C2000Ware Driverlib Files
      2. 4.2 C2000Ware Header Files
      3. 4.3 Linker command Files
      4. 4.4 Minimum Compiler Version Requirement
      5. 4.5 EABI Support
        1. 4.5.1 Flash API
        2. 4.5.2 NoINIT Struct Fix (linker command)
        3. 4.5.3 Pre-Compiled Libraries
    6. 5 References

3.2.5 ROM Code and Peripheral Booting

Both F2837x and F2838x have a boot-ROM that initializes the device upon a reset and then boots to the application based on the boot-mode settings. Many enhancements and new features have been added to the F2838x boot-ROM. However, the default options have been retained between the two devices so that migration between the devices has minimal impact from a device-boot perspective.

Table 10 provides the list of items available in different section of ROM of the F2838x devices.

Table 10. F2838x ROM contents

ROM CPU1 CPU2 CM
UNSECURE
  • Bootloaders
  • IQmath
  • FPU32/FPU64 Math and FFT Tables
  • AES Tables
  • IQmath
  • FPU32/FPU64 Math and FFT Tables
  • AES Tables
---
SECURE
  • Secure Copy Code
  • Secure CRC
  • Secure boot to flash
  • Secure Copy Code
  • Secure CRC
  • Secure boot to flash
  • Secure Copy Code
  • Secure CRC
  • Secure boot to flash
CLA DATAROM
  • Math and FFT Tables
  • Math and FFT Tables
 NA

Table 11 provides a quick comparison of the BOOTMODE option on F2837x vs F2838x.

Table 11. Boot-ROM Comparison

BOOT Feature F2838x F2837x
Default BOOT Pins GPIO72 and GPIO84 GPIO72 and GPIO84
Number of BOOTMODE pins Can be customized to use 0 to 3 boot mode select GPIOs (default 2 BOOTMODE pins) Requires 2 boot mode select GPIOs
Zero BOOTMODE Pin option YES NO
Custom BOOTMODE Up to 8 custom boot mode options can be set in OTP 1 custom boot mode option can be set in OTP
Flash entry point 4 flash entry addresses 1 flash entry address
Reset CPU2 and CM reset are not released to boot until done so by CPU1 application via IPC CPU2 is released out of reset to boot during CPU1 boot
BOOT Support on CPU2 (and CM) Only CPU1 contains bootloaders in ROM YES, CPU1 and CPU2 both contain bootloader in ROM
BOOTMODE setting via USER OTP YES, Z1 and Z2 used for boot OTP config, where Z2 has priority (Z2 is checked before Z1) YES, Z1 and Z2 used for boot OTP config, where Z1 has priority (Z1 checked before Z2)
Wait BOOT
  • Wait BOOT is replaced with CAN BOOT
  • SCI BOOT can be used as Wait BOOT
 YES, dedicated Wait BOOT mode option.
Full IPC library in boot-ROM NO YES
RAM Initialization (Clear all RAMs to 0x0) RAM initialization occurs on POR RAM initialization occurs on POR and XRS
MPOST Support YES NO
SECURE BOOT YES, all three subsystem (CPU1/CPU2 and CM) supports SECURE BOOT NO

For more details about ROM Code and Peripheral Booting, see the TMS320F2838x Microcontrollers Technical Reference Manual.