SPRACR2 March   2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   Enabling Peripheral Expansion Applications Using the HIC
    1.     Trademarks
    2. 1 Introduction
    3. 2 HIC Configurations Overview
      1. 2.1 Access Modes
      2. 2.2 Data Width Selection
      3. 2.3 Base Address Selection
      4. 2.4 Read/write I/O Configuration
      5. 2.5 Device to Host Interrupts
        1. 2.5.1 Device Internal Events
        2. 2.5.2 Software Interrupts
    4. 3 Hardware Considerations
      1. 3.1 Common Signal Names
      2. 3.2 Address Pin Mapping
      3. 3.3 BASESEL Pin Mapping
    5. 4 Example Configuration for Pin Constrained Applications
      1. 4.1 Test Setup
      2. 4.2 Test Description
    6. 5 Example Configuration for Performance-Critical Applications
      1. 5.1 Test Setup
      2. 5.2 Test Description
    7. 6 Handling Device Reset and Low-Power Conditions
    8. 7 References
  2.   A Address Translation for Different Data Width Modes
    1.     A.1 Base Address and Offset Address Configuration

2.4 Read/write I/O Configuration

The HIC supports dual pin and single pin mode for read and write configuration which is controlled by the HICMODECR.RnW register field. In case of dual pin mode, the HIC_nCS acts as the enable pin, whereas, the HIC_nOE for reads and HIC_nWE for writes acts as the strobe/select for each access. Figure 6 shows the timing diagram of the read and write access in dual pin mode.

spracr2-read-and-write-access-in-dual-pin-mode.gifFigure 6. Read and Write Access in Dual Pin Mode

In the single pin mode, the HIC_nCS pin acts as the strobe/select for each access and the HIC_nOE pin acts as a level pin to select read or write. It indicates a read acess when set to 1 and a write access when set to 0. Figure 7 shows the timing diagram of the read and write access in single pin mode.

spracr2-read-and-write-access-in-single-pin-mode.gifFigure 7. Read and Write Access in Single Pin Mode

If the Host memory controller supports strobe timing control of HIC_nCS for each access, the application can take advantage of the single pin mode and free up one pin for other requirements. One example of this mode is the select strobe mode supported by the C2000 External Memory Interface (EMIF) controller.