SPRACU1A October 2020 – June 2021 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6441 , AM6442
The CK and ADDR_CTRL net classes are routed similarly, and are length matched from the DDR controller in the processor to the LPDDR4 SDRAM to minimize skew between the signals and ensure that the ADDR_CTRL signals are properly sampled at the SDRAM. The CK net class requires more care because it runs at a higher transition rate and is differential. The CK and ADDR_CTRL topologies are point-to-point.
Figure 3-4 shows the topology of the CK net class, and Figure 3-5 shows the topology for the corresponding ADDR_CTRL net classes. Length matching requirements for the routing segments are detailed in Table 3-6.
Minimize layer transitions during routing. If a layer transition is necessary, it is preferable to transition to a layer using the same reference plane. If this cannot be accommodated, ensure there are nearby stitching vias to allow the return currents to transition between reference planes when both reference planes are ground or VDDS_DDR. Alternately, ensure there are nearby bypass capacitors to allow the return currents to transition between reference planes when one of the reference planes is ground and the other is VDDS_DDR. This must occur at every reference plane transition. The goal is to minimize the size of the return current path thus minimizing the inductance in this path. Lack of these stitching vias or capacitors results in impedance discontinuities in the signal path that increase crosstalk and signal distortion.
There are no stubs or terminations allowed on the nets of the CK and ADDR_CTRL routing group topologies. All test and probe access points must be in line without any branches or stubs.