SPRACU5C June   2021  – September 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 AM64x Processor Family
    2. 1.2 AM243x Processor Family
  5. 2 Related Collaterals
    1. 2.1 Hardware Design Guide
  6. 3 Processor Selection
    1. 3.1 Data Sheet
    2. 3.2 Peripheral Instance Naming Convention
    3. 3.3 Processor Ordering and Quality
  7. 4 Power Architecture
    1. 4.1 Generating Supply Rails
      1. 4.1.1 PMIC (Power Management IC)
        1. 4.1.1.1 Additional Reference
      2. 4.1.2 Discrete Power
        1. 4.1.2.1 DC/DC Converter
        2. 4.1.2.2 LDO
    2. 4.2 Power
      1. 4.2.1 Load Switch
      2. 4.2.2 eFuse
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (EVM)
    2. 5.2 EVM Versus Data Sheet
      1. 5.2.1 Note About Component Selection
        1. 5.2.1.1 Series Resistor
        2. 5.2.1.2 Parallel Termination
        3. 5.2.1.3 External ESD Protection
      2. 5.2.2 Additional Information
    3. 5.3 Before You Begin The Design
      1. 5.3.1  Documentation
      2. 5.3.2  Processor Pinout Verification
      3. 5.3.3  IOSET
      4. 5.3.4  Note on PADCONFIG Register
      5. 5.3.5  Signal Isolation for Fail-Safe Operation
      6. 5.3.6  Reference to EVM or SK
      7. 5.3.7  Board Design - Layers Optimization
      8. 5.3.8  Termination of Unused Processor Pins
      9. 5.3.9  Naming of Peripheral Instances
      10. 5.3.10 High-Speed Interface Design Guidelines
      11. 5.3.11 Voltage and Thermal Manager (VTM) Module
      12. 5.3.12 Allowed GPIO Current Source or Sink
      13. 5.3.13 Connection of Capacitor to LVCMOS Type IO (Input or Output)
      14. 5.3.14 Processor Related Queries and Clarifications
  9. 6 Processor Specific Recommendations
    1. 6.1 Common (Processor Start-Up) Connection
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Supplies for Core and Peripherals
          1. 6.1.1.1.1 Power Supply Ramp (Slew Rate) Requirement and Dynamic Voltage Scaling
        2. 6.1.1.2 Supply for IO Groups
        3. 6.1.1.3 Supply for VPP (eFuse ROM Programming)
        4. 6.1.1.4 Additional Information
      2. 6.1.2 Capacitors for Supply Rails
        1. 6.1.2.1 Additional Information
      3. 6.1.3 Processor Clock
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 High Frequency Oscillator (MCU_OSC0_XI/ MCU_OSC0_XO)
          2. 6.1.3.1.2 External Clock Input to Main Domain (EXT_REFCLK1)
          3. 6.1.3.1.3 Additional Information
        2. 6.1.3.2 Clock Output
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 Reset Inputs
        2. 6.1.4.2 Reset Status Outputs
        3. 6.1.4.3 Additional Information
      5. 6.1.5 Configuration of Boot Modes (for Processor)
        1. 6.1.5.1 Processor Boot Mode Inputs Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Bootmode Selection
          1. 6.1.5.2.1 Notes for USB Boot Mode
        3. 6.1.5.3 Additional Information
    2. 6.2 Board Debug Using JTAG and EMU
      1. 6.2.1 Additional Information
  10. 7 Processor Peripherals
    1. 7.1 Power Supply Connections for IO Groups
    2. 7.2 Memory Interface (DDR4, LPDDR4, MMCSD (eMMC/SD/SDIO), OSPI/QSPI and GPMC)
      1. 7.2.1 DDR Subsystem (DDRSS)
        1. 7.2.1.1 Double Data Rate 4 (DDR4)
          1. 7.2.1.1.1 Interface Configuration
          2. 7.2.1.1.2 Routing Topology and Terminations
          3. 7.2.1.1.3 Resistors for Control and Calibration
          4. 7.2.1.1.4 Capacitors for the Power Supply Rails
          5. 7.2.1.1.5 Data Bit or Byte Swapping
        2. 7.2.1.2 Low-Power Double Data Rate 4 (LPDDR4)
          1. 7.2.1.2.1 Interface Configuration
          2. 7.2.1.2.2 Routing Topology and Terminations
          3. 7.2.1.2.3 Resistors for Control and Calibration
          4. 7.2.1.2.4 Capacitors for the Power Supply Rails
          5. 7.2.1.2.5 Data Bit or Byte Swapping
      2. 7.2.2 Multi-Media Card/Secure Digital (MMCSD)
        1. 7.2.2.1 MMC0 - eMMC (Embedded Multi-Media Card) Interface
          1. 7.2.2.1.1 MMC0 Used
            1. 7.2.2.1.1.1 IO Power Supply
            2. 7.2.2.1.1.2 eMMC Reset
            3. 7.2.2.1.1.3 Signals Termination
            4. 7.2.2.1.1.4 Capacitors for the Power Supply Rails
          2. 7.2.2.1.2 MMC0 Not Used
          3. 7.2.2.1.3 Additional Information
        2. 7.2.2.2 MMC1 – Secure Digital (SD) Card Interface
          1. 7.2.2.2.1 IO Power Supply
          2. 7.2.2.2.2 SD Card Reset and Boot
          3. 7.2.2.2.3 Signals Termination
          4. 7.2.2.2.4 ESD Protection
          5. 7.2.2.2.5 Capacitors for the Power Supply Rails
        3. 7.2.2.3 Additional Information
      3. 7.2.3 Octal Serial Peripheral Interface (OSPI) or Quad Serial Peripheral Interface (QSPI)
        1. 7.2.3.1 IO Power Supply
        2. 7.2.3.2 OSPI / QSPI Reset
        3. 7.2.3.3 Signals Termination
        4. 7.2.3.4 Loopback Clock
        5. 7.2.3.5 Interface to Multiple Devices
        6. 7.2.3.6 Capacitors for the Power Supply Rails
      4. 7.2.4 General-Purpose Memory Controller (GPMC)
        1. 7.2.4.1 IO Power Supply
        2. 7.2.4.2 GPMC Interface
        3. 7.2.4.3 Memory Reset
        4. 7.2.4.4 Signals Termination
        5. 7.2.4.5 Capacitors for the Power Supply Rails
    3. 7.3 External Communication Interface (Ethernet (CPSW3G and PRU_ICSSG), USB2.0, USB3.0 (SERDES), PCIe (SERDES), UART and CAN)
      1. 7.3.1 Ethernet Interface (CPSW3G and PRU_ICSSG)
        1. 7.3.1.1  IO Power Supply
        2. 7.3.1.2  Media Independent Interface (MAC side)
          1. 7.3.1.2.1 Common Platform Ethernet Switch 3-Port Gigabit (CPSW3G)
          2. 7.3.1.2.2 Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
          3. 7.3.1.2.3 Additional Information
        3. 7.3.1.3  Usage of SysConfig-PinMux Tool
        4. 7.3.1.4  EPHY Reset
        5. 7.3.1.5  Ethernet PHY Pin Strapping
        6. 7.3.1.6  Ethernet PHY (and MAC) Operation and Media Independent Interface (MII) Clock
          1. 7.3.1.6.1 Crystal
          2. 7.3.1.6.2 Oscillator
          3. 7.3.1.6.3 Processor Clock Output (CLKOUT0)
        7. 7.3.1.7  MAC (Data, Control and Clock) Interface Signals Termination
        8. 7.3.1.8  MAC (Media Access Controller) to MAC Interface
        9. 7.3.1.9  Management Data Input/Output (MDIO) Interface
          1. 7.3.1.9.1 MDIO Interface Mode
        10. 7.3.1.10 Ethernet Medium Dependent Interface (MDI) Including Magnetics
        11. 7.3.1.11 Capacitors for the Power Supply Rails
      2. 7.3.2 Universal Serial Bus (USB2.0)
        1. 7.3.2.1 USB Used
          1. 7.3.2.1.1 USB Host Interface
          2. 7.3.2.1.2 USB Device Interface
          3. 7.3.2.1.3 USB Dual-Role Device Interface
          4. 7.3.2.1.4 USB Type-C
        2. 7.3.2.2 USB Not Used
        3. 7.3.2.3 Additional Information
      3. 7.3.3 Serializer/Deserializer (SERDES)
        1. 7.3.3.1 SERDES0 Used
          1. 7.3.3.1.1 USB3SS0 - USB3.0 Super Speed Interface Configuration
            1. 7.3.3.1.1.1 Signal Interface
              1. 7.3.3.1.1.1.1 USB3.0 Super Speed Interface
                1. 7.3.3.1.1.1.1.1 USB3.0 Super Speed Interface Operating Mode Configuration
            2. 7.3.3.1.1.2 Unused SERDES Clock Termination
            3. 7.3.3.1.1.3 Additional Information
          2. 7.3.3.1.2 Peripheral Component Interconnect Express (PCIe) Interface Configuration
            1. 7.3.3.1.2.1 Clock Configuration for PCIe Operating Modes
            2. 7.3.3.1.2.2 Signal Interface Termination
            3. 7.3.3.1.2.3 PCIe Clock (REFCLK) Source
            4. 7.3.3.1.2.4 Hardware Reset (Fundamental Reset)
            5. 7.3.3.1.2.5 PCIe Clock Request (PCIE0_CLKREQn) Signal
            6. 7.3.3.1.2.6 Connecting PCIe Interface Signals
        2. 7.3.3.2 SERDES0 Not Used
      4. 7.3.4 Universal Asynchronous Receiver/Transmitter (UART)
      5. 7.3.5 Controller Area Network (CAN)
    4. 7.4 On-Board Synchronous Communication Interface (MCSPI and I2C)
      1. 7.4.1 Multichannel Serial Peripheral Interface (MCSPI)
      2. 7.4.2 Inter-Integrated Circuit (I2C)
    5. 7.5 Analog to Digital Converter (ADC)
      1. 7.5.1 ADC0 Used
      2. 7.5.2 ADC0 Not Used
    6. 7.6 GPIO and Hardware Diagnostics
      1. 7.6.1 General Purpose Input/Output (GPIO)
        1. 7.6.1.1 Termination and External Buffering
        2. 7.6.1.2 GPIO Multiplexed With MMC Interface
        3. 7.6.1.3 Additional Information
      2. 7.6.2 Internal Hardware Diagnostics
        1. 7.6.2.1 Monitoring of On-Board Supply Voltages Using Processor
          1. 7.6.2.1.1 Voltage Monitor Pins When Used
          2. 7.6.2.1.2 Voltage Monitor Pins Not Used
        2. 7.6.2.2 Internal Temperature Monitoring
        3. 7.6.2.3 Termination of Error Signal Output (MCU_SAFETY_ERRORn)
        4. 7.6.2.4 High Frequency Oscillator (MCU_OSC0) Clock Loss Detection
    7. 7.7 Verifying Board Level Design Issues
      1. 7.7.1 Processor Pin Configuration Using Pinmux Tool
      2. 7.7.2 Schematics Configurations
      3. 7.7.3 Terminations
      4. 7.7.4 Peripheral (Sub System) Clock Outputs
      5. 7.7.5 General Debug
        1. 7.7.5.1 Clock Output for Board Bring-Up, Test or Debug
        2. 7.7.5.2 Additional Information
  11. 8 Layout Notes (to be Added on the Schematic)
  12. 9 Board Design Simulation
  13. 10Additional References
  14. 11Summary
  15. 12References
    1. 12.1 AM64x
    2. 12.2 AM243x
    3. 12.3 Common
  16.   A Terminology
  17.   Revision History
7.3.1.2.1 Common Platform Ethernet Switch 3-Port Gigabit (CPSW3G)

For pin mapping information related to RGMII interface, refer Signal Descriptions, CPSW3G, MAIN Domain, RGMII1 Signal Descriptions and RGMII2 Signal Descriptions sections of the device-specific data sheet.

For pin mapping information related to RMII interface, refer Signal Descriptions, CPSW3G, MAIN Domain, RMII1 and RMII2 Signal Descriptions section of the device-specific data sheet.

Note:

CPSW3G MDIO0, CPSW3G RMII1, CPSW3G RMII2, and CPSW3G RGMII1 have one or more signals which can be multiplexed to more than one pin. Timing requirements and switching characteristics defined in this section are only valid for specific pin combinations known as IOSETs. Valid pin combinations or IOSETs for these interfaces can be found in the tables of the CPSW3G IOSETs section of device-specific data sheet.

Based on the interface required, for information on valid IOSETs, valid pin combinations of each CPSW3G MDIO0 IOSET, CPSW3G RMII1 and RMII2 IOSET, and CPSW3G RGMII1 IOSET, refer Timing and Switching Characteristics, Peripherals, CPSW3G IOSETs section of the device-specific data sheet.

RMII_REF_CLK is common to both RMII1 and RMII2. For proper operation, all pin multiplexed signal assignments must use the same IOSET. Both RMII ports share a single RMII_REF_CLK. This clock can be the input to PRG1_PRU0_GPO10 pin for IOSET1 or the input to PRG1_PRU0_GPO10 pin for IOSET2. All RMII signals must be configured to pins associated with IOSET1 or IOSET2. It is not allowed to split the clock assignment between IOSETs (connecting clock to one of the IOSET and interface signals to the other IOSET). The clock path for each IOSET is timing closed relative to the signals associated with its respective IOSET. The delay difference between the two clock paths are not relative.