SPRACU5C June 2021 – September 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Many of the processor pads support multiplexing of function. This means that their function can be independently chosen from multiple options. The selection of functions available on each pad is enumerated in SIGNAL NAME column in the Pin Attributes table of the device-specific data sheet.
The desired function is selected via the MUXMODE field of the associated pad configuration register. The PADCFG_CTRL0_CFG0_PADCONFIG0 to PADCFG_CTRL0_CFG0_PADCONFIG171 registers control the signal multiplexing of IO modules in the processor Main Domain and MCU_PADCFG_CTRL0_CFG0_PADCONFIG0 to MCU_PADCFG_CTRL0_CFG0_PADCONFIG32 registers control the signal multiplexing of IO modules in the processor MCU Domain.
The Pad Configuration Ball Names table in the Pad Configuration Registers section of the device-specific TRM summarizes the Bit Field Reset Values for all the PADCONFIG registers. Follow the notes added at the end of the table while configuring the PADCONFIG registers. The RXACTIVE bit must never be set without a valid logic state being sourced to the pin associated with the respective PADCONFIG register. This is important since a floating input may damage the processor.