Alternative approach for clocking the Ethernet PHY is to use the processor clock output (CLKOUT0). Clock output is buffered internally and is intended for a point-point clock topology. A series resistor is recommended at the source.

RGMII EPHYs require a 25 MHz clock input that is not synchronous to any other signals. So, this signal will not have any timing requirements, but it is important the EPHY does not receive any non-monotonic transitions on its clock input.

RMII EPHY clocking option changes with the controller (master) and device (slave) configuration.

When configured as controller, most RMII EPHYs require a 25 MHz input clock that is not synchronous to any other signals, the 25 MHz clock signal will not have any timing requirements, but it is important to make sure the EPHY does not receive any non-monotonic transitions on its clock input.

The RMII EPHY provides the 50 MHz clock the MAC. For this use case, the 50 MHz data transfer clock is delayed to the MAC relative to the EPHY. This shifts clock to data timing relationship which may erode the timing margin. This could be problematic for some designs if this delay is too large.

When configured as device, the MAC and the EPHY uses a 50 MHz clock that is synchronous to both transmit and receive data. The 50 MHz clock is defined in the RMII specification as a common data transfer clock signal that is used by both the MAC and the EPHY, where transitions are expected to arrive simultaneously at the MAC and EPHY device pins. This provides better timing margin for both transmit and receive data transfers. It is also important that the MAC and EPHY do not receive any non-monotonic transitions on their clock inputs. To ensure this doesn’t happen, it is highly recommended this clock signal is routed through a two-output phase aligned buffer. Recommend using equal length signal traces that are ½ the length of the data signals for connecting the clock buffer outputs, where one clock output connects to the MAC and the other connects to the EPHY.

For RMII interface, the recommended configuration is the RMII Interface Typical Application (External Clock Source) explained in the device-specific TRM. If RMII Interface Typical Application (Internal Clock Source) configuration explained in the device-specific TRM is used the performance has to be validated on a system level. Provision for an external clock for initial performance testing and comparison is recommended. The Ethernet performance (RGMII) has been validated on the processor and the EPHY with 25 MHz clock.

The CLKOUT0 signal function can be used to source a 25 MHz or a 50 MHz clock to the EPHY. However, this would require the software to configure the clock output. This configuration cannot be used if the board design needs to support Ethernet boot. This clock is likely to glitch anytime the configuration is changed.

The board designer needs to make sure the EPHYs are held in reset for a specified minimum reset hold time after the respective clocks are valid.

TI does not define performance of the processor clock outputs because clock performance is influenced by many variables unique to each system implementation. The board designer will have to validate timing of all peripherals by using their actual PCB delays, min/max output delay characteristics, and min setup/hold requirements of each device to confirm there is enough timing margin.