SPRACU8B August   2021  – January 2023 AM68 , AM68 , AM68A , AM68A , AM69 , AM69 , AM69A , AM69A , DRA821U , DRA821U , DRA829V , DRA829V , TDA4VM , TDA4VM

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Features
      1. 1.1.1 Supported Features (version 0.10.0)
      2. 1.1.2 Unsupported Features (version 0.10.0)
    2. 1.2 Spreadsheet Overview
      1. 1.2.1 Input Worksheets
      2. 1.2.2 Output Worksheets
      3. 1.2.3 Other Worksheets
    3. 1.3 Default SDK Configurations
  4. 2Customizing DDR Configuration
    1. 2.1 Config Worksheet
      1. 2.1.1 System Configuration
      2. 2.1.2 Memory Burst Configuration
    2. 2.2 DRAMTiming Worksheet
      1. 2.2.1 Latency Parameters
      2. 2.2.2 Non-Latency Parameters
    3. 2.3 IO Control Worksheet
      1. 2.3.1 Determining IO Settings
      2. 2.3.2 Processor/DDR Controller IO
      3. 2.3.3 DRAM I/O
  5. 3Software Considerations
    1. 3.1 Updating U-Boot
      1. 3.1.1 Updating DDR Register Settings
      2. 3.1.2 Updating Source to Set Available Memory Size
    2. 3.2 Updating RTOS PDK
      1. 3.2.1 Updating DDR Register Settings
  6. 4Troubleshoot Guide
    1. 4.1 Topics/Issues
      1. 4.1.1 Topic 1
      2. 4.1.2 Topic 2
      3. 4.1.3 Topic 3
  7. 5References
  8.   Revision History

2.2.1 Latency Parameters

As the latency parameters are frequency dependent, each parameter has a unique input for frequency 0 (F0), frequency 1 (F1), and frequency 2 (F2). F0, F1, and F2 are defined by you in the "Config" worksheet. Thus, you should set all three inputs for each latency parameter to correspond with the appropriate value as defined in the specific DDR component data sheet for the given frequency. For example values based on the clock frequency, see Table 100 and Table 167 of JESD209-4D at https://www.jedec.org/system/files/docs/JESD209-4D.pdf. Additional details of each latency parameter can be found in the list below:

  1. Read Latency: This parameter should be set to match the read latency of the DDR at the defined frequency, as well as based on whether read DBI is enabled. Valid input is defined by a drop-down list.
    Note: The drop-down list for read latency is dependent on the user input of the "Data Bus Inversion (Read)" parameter defined in the "Config" worksheet.
  2. Write Latency Set: This parameter defines the write latency set. Valid input is defined by a drop-down list. It is recommended to keep this setting as the default of the tool.
  3. Write Latency: This parameter should be set to match the write latency of the DDR at the defined frequency, as well as based on the write latency set selected. Valid input is defined by a drop-down list.
    Note: The drop-down list for write latency is dependent on the user input of the "Write Latency Set" parameter defined in the "DRAMTiming" worksheet.
  4. Write Recovery: This parameter should be set to match the write recovery time of the DDR at the defined frequency. Valid input is defined by a drop-down list.
  5. ODTLon: This parameter should be set to match the ODTLon latency of the DDR at the defined frequency, as well as based on the write latency set selected. Valid input is defined by a drop-down list.
    Note: The drop-down list for ODTLon is dependent on the user input of the "Write Latency Set" parameter defined in the "DRAMTiming" worksheet.
  6. ODTLoff: This parameter should be set to match the ODTLoff latency of the DDR at the defined frequency, as well as based on the write latency set selected. Valid input is defined by a drop-down list.
    Note: The drop-down list for ODTLoff is dependent on the user input of the "Write Latency Set" parameter defined in the "DRAMTiming" worksheet.