SPRACV1B February   2022  – January 2024 AM2434 , AM6411 , AM6412 , AM6421 , AM6441 , AM6442

 

  1.   Abstract
  2.   2
  3.   Trademarks
  4. 1Introduction
  5. 2Processor Core Benchmarks
    1. 2.1 Dhrystone
    2. 2.2 Trigonometric Functions
  6. 3Compute and Memory System Benchmarks
    1. 3.1 Memory Bandwidth and Latency
      1. 3.1.1 LMBench
      2. 3.1.2 STREAM
      3. 3.1.3 Cortex-R5 Memory Access Latency
    2. 3.2 CoreMark®-Pro
    3. 3.3 Fast Fourier Transform
    4. 3.4 Cryptographic Benchmarks
  7. 4Application Benchmarks
    1. 4.1 Machine Learning Inference
    2. 4.2 Field Oriented Control (FOC) Loop
    3. 4.3 PCIE to DDR Performance Using BCDMA
      1. 4.3.1 Test Setup
      2. 4.3.2 Result and Observation
    4. 4.4 DDR to DDR Performance Using BCDMA
      1. 4.4.1 Test Setup
      2. 4.4.2 Result and Observation
  8. 5References
  9. 6Revision History

4.4 DDR to DDR Performance Using BCDMA

AM64x MCU+ SDK contains UDMA-based examples.

Here we have used these to measure transfer performance (in terms of bandwidth) from DDR to DDR using BCDMA and multiple channels in parallel.

Hardware Details:

Software Details:

Note: By default in MCU+ SDK, maximum 4 UDMA channels can be assigned to R5F_0_0 core.

To test more channels than the default configuration:

  • Use the resource management (RM) tool to manage UDMA channel allocation to the cores.
  • Add number of UDMA channels, using "example.syscfg" file in the imported CCS project