SPRACV1B February   2022  – January 2024 AM2434 , AM6411 , AM6412 , AM6421 , AM6441 , AM6442

 

  1.   Abstract
  2.   2
  3.   Trademarks
  4. 1Introduction
  5. 2Processor Core Benchmarks
    1. 2.1 Dhrystone
    2. 2.2 Trigonometric Functions
  6. 3Compute and Memory System Benchmarks
    1. 3.1 Memory Bandwidth and Latency
      1. 3.1.1 LMBench
      2. 3.1.2 STREAM
      3. 3.1.3 Cortex-R5 Memory Access Latency
    2. 3.2 CoreMark®-Pro
    3. 3.3 Fast Fourier Transform
    4. 3.4 Cryptographic Benchmarks
  7. 4Application Benchmarks
    1. 4.1 Machine Learning Inference
    2. 4.2 Field Oriented Control (FOC) Loop
    3. 4.3 PCIE to DDR Performance Using BCDMA
      1. 4.3.1 Test Setup
      2. 4.3.2 Result and Observation
    4. 4.4 DDR to DDR Performance Using BCDMA
      1. 4.4.1 Test Setup
      2. 4.4.2 Result and Observation
  8. 5References
  9. 6Revision History

4.2 Field Oriented Control (FOC) Loop

The MCU+ and Linux SDKs contain a benchmark demo application that includes an example FOC loop implementing the algorithm shown in Figure 4-1 and displaying the performance of the loop. Functions in the include Clark, Park, inverse Park, Sin, Cos, PI controllers and space vector generation.

GUID-B8C630B3-5938-453F-BE1E-D9B0F615FC00-low.gifFigure 4-1 Speed Closed Field Oriented Control Loop

The performance of the FOC loop on a single Arm Cortex -R5F core of AM64x is shown in the table below. Each of the up to four Arm Cortex-R5F core can independently achieve this performance for the motor it is controlling.

FOC Loop Execution Time (microseconds)
Average0.4