SPRACV2 November   2020 AWR1843 , AWR2243

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background – Simple Single-Chip Applications
  3. 2Cascade Incoherence Sources and Mitigation Strategies
    1. 2.1 PCB Routing Imbalances and Device Processes
    2. 2.2 Temperature Drifts
    3. 2.3 Scheduling of Run Time Calibrations
  4. 3Enabling Cascade Coherence and Improved Phase Performance
    1. 3.1 High-Level Summary
      1. 3.1.1 Sequence of Proposed Steps and Introductory Flow Diagrams
    2. 3.2 Saving RF INIT Calibration Results at Customer Factory
      1. 3.2.1 Note on LODIST Calibration
      2. 3.2.2 TX Phase Shifter Calibration and Saving Results at Customer Factory
    3. 3.3 Corner Reflector-Based Offsets Measurement at Customer Factory
      1. 3.3.1 Corner Reflector-Based Inter-Channel Imbalances
      2. 3.3.2 Corner Reflector-Based TX Phase Shifter Errors
    4. 3.4 Restoring Customer Calibration Results In-Field
      1. 3.4.1 Restore RF INIT Calibrations Results In-Field
      2. 3.4.2 Restore TX Phase Shift Calibration Results In-Field
    5. 3.5 Host-Based Temperature Calibrations In-Field
      1. 3.5.1 Disabling AWR Devices’ Autonomous Run Time Calibrations
      2. 3.5.2 Enabling Host-Based Temperature Calibrations of Inter-Channel Imbalances
      3. 3.5.3 Switching of DSP Imbalance Data
      4. 3.5.4 Enabling TX Phase Shifter’s Host-Based Temperature Calibrations
        1. 3.5.4.1 Estimating TX Phase Shift Values at Any Temperature
        2. 3.5.4.2 Temperature Correction LUTs for AWR1843TX Phase Shifter
        3. 3.5.4.3 Temperature Correction LUTs for AWR2243 TX Phase Shifter
        4. 3.5.4.4 Restoring TX Phase Shift Values – Format Conversion
        5. 3.5.4.5 Restoring TX Phase Shift Values – Transition Timing and Constraints
        6. 3.5.4.6 Typical Post-Calibration TX Phase Shifter Accuracies
        7. 3.5.4.7 Correcting for Temperature Drift While Sweeping Across Phase Settings
        8. 3.5.4.8 Amplitude Stability Across Phase Shifter Settings
        9. 3.5.4.9 Impact of Customer PCB’s 20-GHz Sync Path Attenuation on TX Phase Shifters
      5. 3.5.5 Ambient and Device Temperatures
  5. 4Concept Illustrations
  6. 5Miscellaneous (Interference, Gain Variation, Sampling Jitter)
    1. 5.1 Handling Interference In-Field
    2. 5.2 Information on TX Power and RX Gain Drift with Temperature
    3. 5.3 Jitter Between Chirp Start and ADC Sampling Start
  7. 6Conclusion
  8.   A Appendix
    1.     A.1 Terminology
    2.     A.2 References
    3.     A.3 Flow Diagrams for Proposed Cascade Coherence Scheme
    4.     A.4 LUTs for TX Phase Shifter Temperature Drift Mitigation
    5.     A.5 Circular Shift of TX Phase Shifter Calibration Data Save and Restore APIs

3.5.4.9 Impact of Customer PCB’s 20-GHz Sync Path Attenuation on TX Phase Shifters

In the AWR2243 cascade system, the 20-GHz LO signal from ClockOut or SyncOut pin of Master is routed on the PCB and fed to the SyncIn pin of all the devices, to achieve RF synchronization. This PCB routing can lead to losses in the 20-GHz Sync Path, and the change in 20-GHz SyncIn power level can indirectly change the TX Phase Shifter properties.

In TI lab evaluation of few devices across DoE process corners and temperature, with SyncIn BGA power set at approximately -0.5 dBm to -4.5 dBm, the change observed in PS INL with all the above recommended procedures and LUTs has been observed to be <1 degree across all phase shifter settings.

Because the 20-GHz power levels are highly dependent on the customer’s PCB design, if further TX phase shifter accuracy improvement is desired, the customer may consider characterizing the TX phase shifter over temperature across several of their own sensors, re-evaluating and re-deriving the LUTs mentioned in this note corresponding to their own sensor.