The previous section demonstrate that almost all of the charging or discharging of the S+H capacitor C_H in a dedicated ADC configuration comes from charge equalization, so a S+H value near the minimum value supported by the ADC can be used (since the charge equalization occurs quickly at the beginning of the S+H window). Furthermore, re-running the simulation in Figure 4-3, but with progressively increasing values of the capacitor on the ADC pin will result in progressively better settling performance at each sampling step (not shown). Therefore, it is generally desirable to maximize the size of C_S (if this can be changed in the system hardware) as this will maximize the settling performance. However, note that the source impedance, R_s, and the ADC pin capacitance, C_s form a low-pass filter. Therefore, the size of C_s will need to be limited to ensure the input circuit has sufficient bandwidth to not distort the signal of interest.

These design decisions are summarized in the following list:

• Isolate the signal affected by memory cross-talk to a dedicated ADC
• S+H window duration can be set to the minimum allowed by the ADC (or any other valid convenient value)
• If possible, modify the circuit to maximize C_s (the capacitance on the ADC pin) being mindful that the input circuit bandwidth (BW_RsCs) needs to be large enough to allow the circuit to sense the frequencies of interest in the input signal.

• (Optional) Simulate the settling performance at frequencies of interest (see next section)