SPRACX6 June 2021 DRA821U , DRA821U , DRA821U-Q1 , DRA821U-Q1 , DRA829J , DRA829J , DRA829J-Q1 , DRA829J-Q1 , DRA829V , DRA829V , DRA829V-Q1 , DRA829V-Q1 , TDA4VM , TDA4VM , TDA4VM-Q1 , TDA4VM-Q1
All modules and subsystems on the Jacinto7 interconnect can be classified into two categories: masters and slaves. Masters are capable of initiating read and write transfers in the system. The slaves on the other hand depend on the masters to perform transfers to and from them.