SPRACX6 June   2021 DRA821U , DRA821U , DRA821U-Q1 , DRA821U-Q1 , DRA829J , DRA829J , DRA829J-Q1 , DRA829J-Q1 , DRA829V , DRA829V , DRA829V-Q1 , DRA829V-Q1 , TDA4VM , TDA4VM , TDA4VM-Q1 , TDA4VM-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Firewall Documentation
    1. 2.1 Technical Reference Manual (TRM)
    2. 2.2 SDK TISCI Documentation
    3. 2.3 SDK Firewall Documentation
    4. 2.4 TI NDA Firewall Slide Sets
  4. 3Firewall Definitions and Terms
  5. 4SysConfig Tool
  6. 5Master Firewall versus Slave Firewall
    1. 5.1 Slave Firewalls
    2. 5.2 Master Firewalls
    3. 5.3 A72 Master Firewall
  7. 6Where to Firewall
    1. 6.1 Example
  8. 7Programming Firewalls
    1. 7.1 Sample SBL Code
      1. 7.1.1 Create a Table
      2. 7.1.2 Parse the Table of Firewall Regions
      3. 7.1.3 Utility Functions
      4. 7.1.4 Processor SDK 7.1 SBL Example

5.3 A72 Master Firewall

The A72 itself is a master on the interconnect and has a master side firewall capable of filtering outgoing transactions. Figure 5-1 (available in the Technical Reference for the DRA829 / TDA4 device) shows where the firewall to be programmed is located.

The master side firewall for the A72 has a Firewall Id of 257, as seen in below code example as CSL_MSTR_FW_A72SS0_CORE0_CPU_0_CPU_0_MSMC_ID.

GUID-20210504-CA0I-3L5X-KTKW-XKHP29HXMZBQ-low.jpg Figure 5-1 COMPUTE_CLUSTER0 Overview