SPRACX6 June   2021 DRA821U , DRA821U , DRA821U-Q1 , DRA821U-Q1 , DRA829J , DRA829J , DRA829J-Q1 , DRA829J-Q1 , DRA829V , DRA829V , DRA829V-Q1 , DRA829V-Q1 , TDA4VM , TDA4VM , TDA4VM-Q1 , TDA4VM-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Firewall Documentation
    1. 2.1 Technical Reference Manual (TRM)
    2. 2.2 SDK TISCI Documentation
    3. 2.3 SDK Firewall Documentation
    4. 2.4 TI NDA Firewall Slide Sets
  4. 3Firewall Definitions and Terms
  5. 4SysConfig Tool
  6. 5Master Firewall versus Slave Firewall
    1. 5.1 Slave Firewalls
    2. 5.2 Master Firewalls
    3. 5.3 A72 Master Firewall
  7. 6Where to Firewall
    1. 6.1 Example
  8. 7Programming Firewalls
    1. 7.1 Sample SBL Code
      1. 7.1.1 Create a Table
      2. 7.1.2 Parse the Table of Firewall Regions
      3. 7.1.3 Utility Functions
      4. 7.1.4 Processor SDK 7.1 SBL Example

7 Programming Firewalls

Note that all programming of firewall register is done via TISCI. There is no direct register programming of firewall registers on the Jacinto 7 family of devices.

Not all firewalls are user programmable. For firewalls that are programmable, you can use available TI documentation or make use of the sample code below.

There are numerous examples in the Processor SDK showing firewalls being programmed, as well, the aforementioned TI Documentation has lots of information.

The sample code below is targeted at preventing A72 from accessing certain DDR memory regions. There will be many different use cases, to allow or prevent access to memory locations or modules. Each of these scenarios can be handled by the below sample framework, by simply expanding the table entries.